PIC16C7X 8-Bit CMOS Microcontrollers with A/D Converter * Wide operating voltage range: 2.5V to 6.0V * High Sink/Source Current 25/25 mA * Commercial, Industrial and Extended temperature ranges * Low-power consumption: * < 2 mA @ 5V, 4 MHz * 15 A typical @ 3V, 32 kHz * < 1 A typical standby current Devices included in this data sheet: * PIC16C72 * PIC16C74A * PIC16C73 * PIC16C76 * PIC16C73A * PIC16C77 * PIC16C74 PIC16C7X Microcontroller Core Features: * High-performance RISC CPU * Only 35 single word instructions to learn * All single cycle instructions except for program branches which are two cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * Up to 8K x 14 words of Program Memory, up to 368 x 8 bytes of Data Memory (RAM) * Interrupt capability * Eight level deep hardware stack * Direct, indirect, and relative addressing modes * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Selectable oscillator options * Low-power, high-speed CMOS EPROM technology * Fully static design PIC16C7X Features PIC16C7X Peripheral Features: * Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Capture, Compare, PWM module(s) * Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM max. resolution is 10-bit * 8-bit multichannel analog-to-digital converter * Synchronous Serial Port (SSP) with SPI and I2C * Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) * Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls * Brown-out detection circuitry for Brown-out Reset (BOR) 72 73 73A 74 74A 76 77 Program Memory (EPROM) x 14 2K 4K 4K 4K 4K 8K 8K Data Memory (Bytes) x 8 128 192 192 192 192 368 368 I/O Pins 22 22 22 33 33 22 33 Parallel Slave Port -- -- -- Yes Yes -- Yes Capture/Compare/PWM Modules 1 2 2 2 2 2 2 Timer Modules 3 3 3 3 3 3 3 A/D Channels 5 5 5 8 8 5 8 SPI/I2C SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Yes Brown-out Reset Yes -- Yes -- Yes Yes Yes Interrupt Sources 8 11 11 12 12 11 12 Serial Communication 1997 Microchip Technology Inc. DS30390E-page 1 PIC16C7X Pin Diagrams SDIP, SOIC, Windowed Side Brazed Ceramic SSOP *1 28 RB7 MCLR/VPP *1 28 RB7 RA0/AN0 2 27 RB6 RA0/AN0 2 27 RB6 RA1/AN1 3 26 RB5 RA1/AN1 3 26 RB5 RA2/AN2 4 25 RB4 RA2/AN2 4 25 RB4 RA3/AN3/VREF 5 24 RB3 RA3/AN3/VREF 5 24 RB3 RA4/T0CKI 6 23 RB2 RA4/T0CKI 6 23 RB2 RA5/SS/AN4 VSS 7 8 22 21 RB1 RB0/INT RA5/SS/AN4 VSS 7 8 22 21 RB1 RB0/INT OSC1/CLKIN MCLR/VPP 9 20 VDD OSC1/CLKIN 9 20 VDD OSC2/CLKOUT 10 19 VSS OSC2/CLKOUT 10 19 VSS RC0/T1OSO/T1CKI 11 18 RC7 RC0/T1OSO/T1CKI 11 18 RC7 RC1/T1OSI 12 17 RC6 RC1/T1OSI 12 17 RC6 RC2/CCP1 13 16 RC5/SDO RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA RC3/SCK/SCL 14 15 RC4/SDI/SDA PIC16C72 PIC16C72 SDIP, SOIC, Windowed Side Brazed Ceramic *1 28 RB7 RA0/AN0 2 27 RB6 RA1/AN1 3 26 RB5 MCLR/VPP RA2/AN2 4 25 RB4 RA3/AN3/VREF 5 24 RB3 RA4/T0CKI 6 23 RB2 RA5/SS/AN4 VSS 7 8 22 21 RB1 RB0/INT OSC1/CLKIN 9 20 VDD OSC2/CLKOUT 10 19 VSS RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA PIC16C73 PIC16C73A PIC16C76 DS30390E-page 2 PDIP, Windowed CERDIP MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 PIC16C74 PIC16C74A PIC16C77 1997 Microchip Technology Inc. PIC16C7X 1 2 3 4 5 6 7 8 9 10 11 PIC16C74 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/SS/AN4 RA4/T0CKI MQFP TQFP RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 PIC16C74A PIC16C77 12 13 14 15 16 17 18 19 20 21 22 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF PIC16C74 PIC16C74A PIC16C77 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC RA4/T0CKI RA5/SS/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC 44 43 42 41 40 39 38 37 36 35 34 6 5 4 3 2 1 44 43 42 41 40 PLCC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF 12 13 14 15 16 17 18 19 20 21 22 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 MQFP RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC Pin Diagrams (Cont.'d) 1997 Microchip Technology Inc. 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/SS/AN4 RA4/T0CKI DS30390E-page 3 PIC16C7X Table of Contents 1.0 General Description ....................................................................................................................................................................... 5 2.0 PIC16C7X Device Varieties ........................................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................... 9 4.0 Memory Organization................................................................................................................................................................... 19 5.0 I/O Ports....................................................................................................................................................................................... 43 6.0 Overview of Timer Modules ......................................................................................................................................................... 57 7.0 Timer0 Module ............................................................................................................................................................................. 59 8.0 Timer1 Module ............................................................................................................................................................................. 65 9.0 Timer2 Module ............................................................................................................................................................................. 69 10.0 Capture/Compare/PWM Module(s).............................................................................................................................................. 71 11.0 Synchronous Serial Port (SSP) Module....................................................................................................................................... 77 12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ...................................................................................... 99 13.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117 14.0 Special Features of the CPU ..................................................................................................................................................... 129 15.0 Instruction Set Summary............................................................................................................................................................ 147 16.0 Development Support ................................................................................................................................................................ 163 17.0 Electrical Characteristics for PIC16C72 ..................................................................................................................................... 167 18.0 Electrical Characteristics for PIC16C73/74................................................................................................................................ 183 19.0 Electrical Characteristics for PIC16C73A/74A ........................................................................................................................... 201 20.0 Electrical Characteristics for PIC16C76/77................................................................................................................................ 219 21.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 241 22.0 Packaging Information ............................................................................................................................................................... 251 Appendix A: ................................................................................................................................................................................... 263 Appendix B: Compatibility ............................................................................................................................................................. 263 Appendix C: What's New............................................................................................................................................................... 264 Appendix D: What's Changed ....................................................................................................................................................... 264 Appendix E: PIC16/17 Microcontrollers ....................................................................................................................................... 265 Pin Compatibility ................................................................................................................................................................................ 271 Index .................................................................................................................................................................................................. 273 List of Examples................................................................................................................................................................................. 279 List of Figures..................................................................................................................................................................................... 280 List of Tables...................................................................................................................................................................................... 283 Reader Response .............................................................................................................................................................................. 286 PIC16C7X Product Identification System........................................................................................................................................... 287 For register and module descriptions in this data sheet, device legends show which devices apply to those sections. As an example, the legend below would mean that the following section applies only to the PIC16C72, PIC16C73A and PIC16C74A devices. Applicable Devices 72 73 73A 74 74A 76 77 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. DS30390E-page 4 1997 Microchip Technology Inc. PIC16C7X 1.0 GENERAL DESCRIPTION The PIC16C7X is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16CXX mid-range family. All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16CXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C72 has 128 bytes of RAM and 22 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/ PWM module and one serial port. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. Also a 5-channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. The PIC16C73/73A devices have 192 bytes of RAM, while the PIC16C76 has 368 byes of RAM. Each device has 22 I/O pins. In addition, several peripheral features are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial Communications Interface or SCI. Also a 5-channel high-speed 8-bit A/ D is provided.The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. The PIC16C74/74A devices have 192 bytes of RAM, while the PIC16C77 has 368 bytes of RAM. Each device has 33 I/O pins. In addition several peripheral features are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial Communications Interface or SCI. An 8-bit Parallel Slave Port is provided. Also an 8-channel high-speed 1997 Microchip Technology Inc. 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc. The PIC16C7X family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup. A UV erasable CERDIP packaged version is ideal for code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production in any volume. The PIC16C7X family fits perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C7X very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, serial communication, capture and compare, PWM functions and coprocessor applications). 1.1 Family and Upward Compatibility Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to the PIC16CXX family of devices (Appendix B). 1.2 Development Support PIC16C7X devices are supported by the complete line of Microchip Development tools. Please refer to Section 16.0 for more details about Microchip's development tools. DS30390E-page 5 PIC16C7X TABLE 1-1: PIC16C7XX FAMILY OF DEVCES PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72(1) Maximum Frequency of Operation (MHz) 20 20 20 20 20 20 EPROM Program Memory (x14 words) 512 1K 1K 2K 2K -- ROM Program Memory (14K words) -- -- -- -- -- 2K Data Memory (bytes) 36 36 68 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/ Peripherals PWM Module(s) -- -- -- -- 1 1 Serial Port(s) (SPI/I2C, USART) -- -- -- -- SPI/I2C SPI/I2C Parallel Slave Port -- -- Clock Memory Features -- -- -- -- A/D Converter (8-bit) Channels 4 4 4 4 5 5 Interrupt Sources 4 4 4 4 8 8 I/O Pins 13 13 13 13 22 22 Voltage Range (Volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Brown-out Reset Yes -- Yes Yes Yes Yes Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP, SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP PIC16C74A PIC16C73A Clock Memory PIC16C77 Maximum Frequency of Oper- 20 ation (MHz) 20 20 20 EPROM Program Memory (x14 words) 4K 4K 8K 8K Data Memory (bytes) 192 192 368 368 Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 2 2 2 Serial Port(s) (SPI/I2C, US- SPI/I2C, USART ART) SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART Parallel Slave Port Yes -- Yes 8 5 8 Capture/Compare/PWM Mod- 2 Peripherals ule(s) -- A/D Converter (8-bit) Channels 5 Features PIC16C76 Interrupt Sources 11 12 11 12 I/O Pins 22 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Brown-out Reset Yes Yes Yes Yes Packages 28-pin SDIP, SOIC 40-pin DIP; 44-pin PLCC, MQFP, TQFP 28-pin SDIP, SOIC 40-pin DIP; 44-pin PLCC, MQFP, TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices. DS30390E-page 6 1997 Microchip Technology Inc. PIC16C7X 2.0 PIC16C7X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C7X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C7X family, there are two device "types" as indicated in the device number: 1. 2. 2.1 C, as in PIC16C74. These devices have EPROM type memory and operate over the standard voltage range. LC, as in PIC16LC74. These devices have EPROM type memory and operate over an extended voltage range. UV Erasable Devices The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password, or ID number. Microchip's PICSTART Plus and PRO MATE II programmers both support programming of the PIC16C7X. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. 1997 Microchip Technology Inc. DS30390E-page 7 PIC16C7X NOTES: DS30390E-page 8 1997 Microchip Technology Inc. PIC16C7X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35) execute in a single cycle (200 ns @ 20 MHz) except for program branches. The table below lists program memory (EPROM) and data memory (RAM) for each PIC16C7X device. Device PIC16C72 PIC16C73 PIC16C73A PIC16C74 PIC16C74A PIC16C76 PIC16C77 Program Memory 2K x 14 4K x 14 4K x 14 4K x 14 4K x 14 8K x 14 8K x 14 PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. Data Memory 128 x 8 192 x 8 192 x 8 192 x 8 192 x 8 368 x 8 386 x 8 The PIC16CXX can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly. 1997 Microchip Technology Inc. DS30390E-page 9 PIC16C7X FIGURE 3-1: PIC16C72 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 RAM File Registers 128 x 8 8 Level Stack (13-bit) 2K x 14 8 Data Bus Program Counter EPROM RAM Addr(1) PORTB 9 Addr MUX Instruction reg 7 Direct Addr 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 3 Power-up Timer Oscillator Start-up Timer Instruction Decode & Control Power-on Reset Timing Generation ALU MCLR RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 8 Watchdog Timer Brown-out Reset OSC1/CLKIN OSC2/CLKOUT MUX PORTC W reg VDD, VSS Timer0 Timer1 Timer2 A/D Synchronous Serial Port CCP1 Note 1: Higher order bits are from the STATUS register. DS30390E-page 10 1997 Microchip Technology Inc. PIC16C7X FIGURE 3-2: Device PIC16C73/73A/76 BLOCK DIAGRAM Program Memory Data Memory (RAM) PIC16C73 PIC16C73A PIC16C76 4K x 14 4K x 14 8K x 14 192 x 8 192 x 8 368 x 8 13 8 Data Bus Program Counter PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 EPROM Program Memory Program Bus RAM File Registers 8 Level Stack (13-bit) 14 RAM Addr(1) PORTB 9 Addr MUX Instruction reg 7 Direct Addr 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 3 MUX Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Timing Generation Watchdog Timer Brown-out Reset(2) OSC1/CLKIN OSC2/CLKOUT Power-on Reset MCLR ALU PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8 W reg VDD, VSS Timer0 Timer1 Timer2 A/D CCP1 CCP2 Synchronous Serial Port USART Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C73. 1997 Microchip Technology Inc. DS30390E-page 11 PIC16C7X FIGURE 3-3: Device PIC16C74/74A/77 BLOCK DIAGRAM Program Memory Data Memory (RAM) PIC16C74 PIC16C74A PIC16C77 4K x 14 4K x 14 8K x 14 192 x 8 192 x 8 368 x 8 13 8 Data Bus Program Counter PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 EPROM Program Memory Program Bus RAM File Registers 8 Level Stack (13-bit) 14 RAM Addr (1) PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT MUX ALU PORTD 8 Watchdog Timer Brown-out Reset(2) W reg RD7/PSP7:RD0/PSP0 Parallel Slave Port MCLR PORTC VDD, VSS PORTE RE0/RD/AN5 RE1/WR/AN6 Timer0 Timer1 Timer2 A/D CCP1 CCP2 Synchronous Serial Port USART RE2/CS/AN7 Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C74. DS30390E-page 12 1997 Microchip Technology Inc. PIC16C7X TABLE 3-1: PIC16C72 PINOUT DESCRIPTION DIP Pin# SSOP Pin# SOIC Pin# I/O/P Type OSC1/CLKIN 9 9 9 I OSC2/CLKOUT 10 10 10 O -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 1 1 I/P ST RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI 2 3 4 5 6 2 3 4 5 6 2 3 4 5 6 I/O I/O I/O I/O I/O TTL TTL TTL TTL ST RA5/SS/AN4 7 7 7 I/O TTL RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 21 22 23 24 25 26 27 28 21 22 23 24 25 26 27 28 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0 RA1 can also be analog input1 RA2 can also be analog input2 RA3 can also be analog input3 or analog reference voltage RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0 can also be the external interrupt pin. RC0/T1OSO/T1CKI 11 11 11 I/O ST RC1/T1OSI RC2/CCP1 12 13 12 13 12 13 I/O I/O ST ST RC3/SCK/SCL 14 14 14 I/O ST RC4/SDI/SDA 15 15 15 I/O ST Pin Name RC5/SDO RC6 RC7 VSS VDD Legend: I = input Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1 can also be the Timer1 oscillator input. RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5 can also be the SPI Data Out (SPI mode). 16 16 16 I/O ST 17 17 17 I/O ST 18 18 18 I/O ST 8, 19 8, 19 8, 19 P -- Ground reference for logic and I/O pins. 20 20 20 P -- Positive supply for logic and I/O pins. O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1997 Microchip Technology Inc. DS30390E-page 13 PIC16C7X TABLE 3-2: PIC16C73/73A/76 PINOUT DESCRIPTION DIP Pin# SOIC Pin# I/O/P Type OSC1/CLKIN 9 9 I OSC2/CLKOUT 10 10 O -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 1 I/P ST RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI 2 3 4 5 6 2 3 4 5 6 I/O I/O I/O I/O I/O TTL TTL TTL TTL ST RA5/SS/AN4 7 7 I/O TTL RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 21 22 23 24 25 26 27 28 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 can also be analog input0 RA1 can also be analog input1 RA2 can also be analog input2 RA3 can also be analog input3 or analog reference voltage RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0 can also be the external interrupt pin. Pin Name Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. Interrupt on change pin. Interrupt on change pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. VSS 8, 19 8, 19 P -- Ground reference for logic and I/O pins. VDD 20 20 P -- Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. DS30390E-page 14 1997 Microchip Technology Inc. PIC16C7X TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION DIP Pin# PLCC Pin# QFP Pin# I/O/P Type OSC1/CLKIN 13 14 30 I OSC2/CLKOUT 14 15 31 O -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0 RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1 RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5/SS/AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. Pin Name Buffer Type Description ST/CMOS(4) Oscillator crystal input/external clock source input. PORTA is a bi-directional I/O port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST(1) RB1 34 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3 36 39 11 I/O TTL RB4 37 41 14 I/O TTL Interrupt on change pin. RB5 38 42 15 I/O TTL Interrupt on change pin. I/O TTL/ST(2) RB6 39 43 16 RB0 can also be the external interrupt pin. Interrupt on change pin. Serial programming clock. 40 44 17 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. RB7 Legend: I = input Note 1: 2: 3: 4: 1997 Microchip Technology Inc. DS30390E-page 15 PIC16C7X TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION (Cont.'d) Pin Name DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus. RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 19 20 21 22 27 28 29 30 21 22 23 24 30 31 32 33 38 39 40 41 2 3 4 5 I/O I/O I/O I/O I/O I/O I/O I/O ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) ST/TTL(3) RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE0 can also be read control for the parallel slave port, or analog input5. RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel slave port, or analog input6. RE2/CS/AN7 10 11 27 I/O ST/TTL(3) 12,31 11,32 -- 13,34 12,35 1,17,28, 40 6,29 7,28 12,13, 33,34 P P -- -- -- RE2 can also be select control for the parallel slave port, or analog input7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected. PORTE is a bi-directional I/O port. VSS VDD NC Legend: I = input Note 1: 2: 3: 4: O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. DS30390E-page 16 1997 Microchip Technology Inc. PIC16C7X 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-4. Instruction Flow/Pipelining An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase clock Q3 Q4 PC OSC2/CLKOUT (RC mode) EXAMPLE 3-1: PC PC+1 Fetch INST (PC) Execute INST (PC-1) PC+2 Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) INSTRUCTION PIPELINE FLOW 1. MOVLW 55h Tcy0 Tcy1 Fetch 1 Execute 1 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 Fetch 2 Tcy2 Tcy3 Tcy4 Tcy5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. 1997 Microchip Technology Inc. DS30390E-page 17 PIC16C7X NOTES: DS30390E-page 18 1997 Microchip Technology Inc. PIC16C7X 4.0 MEMORY ORGANIZATION FIGURE 4-2: Applicable Devices 72 73 73A 74 74A 76 77 Program Memory Organization The PIC16C7X family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The amount of program memory available to each device is listed below: Device Program Memory Address Range CALL, RETURN RETFIE, RETLW 13 Stack Level 1 Stack Level 8 PIC16C72 2K x 14 0000h-07FFh PIC16C73 4K x 14 0000h-0FFFh PIC16C73A 4K x 14 0000h-0FFFh PIC16C74 4K x 14 0000h-0FFFh PIC16C74A 4K x 14 0000h-0FFFh PIC16C76 8K x 14 0000h-1FFFh PIC16C77 8K x 14 0000h-1FFFh For those devices with less than 8K program memory, accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 4-1: PC<12:0> PIC16C72 PROGRAM MEMORY MAP AND STACK User Memory Space 4.1 PIC16C73/73A/74/74A PROGRAM MEMORY MAP AND STACK Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory (Page 0) 07FFh On-chip Program Memory (Page 1) 0800h 0FFFh 1000h 1FFFh PC<12:0> CALL, RETURN RETFIE, RETLW 13 Stack Level 1 User Memory Space Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory 07FFh 0800h 1FFFh 1997 Microchip Technology Inc. DS30390E-page 19 PIC16C7X FIGURE 4-3: PIC16C76/77 PROGRAM MEMORY MAP AND STACK 4.2 Applicable Devices 72 73 73A 74 74A 76 77 PC<12:0> CALL, RETURN RETFIE, RETLW The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. 13 Stack Level 1 RP1:RP0 (STATUS<6:5>) = 00 Bank0 = 01 Bank1 = 10 Bank2 = 11 Bank3 Stack Level 2 User Memory Space Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h On-Chip On-Chip On-Chip Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some "high use" special function registers from one bank may be mirrored in another bank for code reduction and quicker access. Page 0 07FFh 0800h Page 1 0FFFh 1000h On-Chip Data Memory Organization 4.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 4.5). Page 2 Page 3 17FFh 1800h 1FFFh DS30390E-page 20 1997 Microchip Technology Inc. PIC16C7X FIGURE 4-4: PIC16C72 REGISTER FILE MAP File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC PCLATH INTCON PIR1 PCLATH INTCON PIE1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON PCON ADRES ADCON0 General Purpose Register PR2 SSPADD SSPSTAT ADCON1 General Purpose Register FIGURE 4-5: File Address File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h A0h PIC16C73/73A/74/74A REGISTER FILE MAP File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE(2) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 General Purpose Register BFh C0h INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD(2) TRISE(2) PCLATH INTCON PIE1 PIE2 PCON PR2 SSPADD SSPSTAT TXSTA SPBRG ADCON1 General Purpose Register FFh 7Fh Bank 0 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h Bank 1 FFh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 1997 Microchip Technology Inc. Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These registers are not physically implemented on the PIC16C73/73A, read as '0'. DS30390E-page 21 PIC16C7X FIGURE 4-6: PIC16C76/77 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD (1) PORTE (1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register Indirect addr.(*) OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD (1) TRISE (1) PCLATH INTCON PIE1 PIE2 PCON PR2 SSPADD SSPSTAT TXSTA SPBRG ADCON1 accesses 70h-7Fh 7Fh Bank 0 Indirect addr.(*) TMR0 PCL STATUS FSR PORTB PCLATH INTCON General Purpose Register 16 Bytes A0h General Purpose Register 80 Bytes 96 Bytes 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh EFh F0h FFh Bank 1 General Purpose Register 80 Bytes accesses 70h-7Fh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION PCL STATUS FSR TRISB PCLATH INTCON General Purpose Register 16 Bytes 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register 80 Bytes 16Fh 170h accesses 70h - 7Fh 17Fh 1EFh 1F0h 1FFh Bank 3 Bank 2 Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: PORTD, PORTE, TRISD, and TRISE are unimplemented on the PIC16C76, read as '0'. Note: DS30390E-page 22 The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require relocation of data memory usage in the user application code if upgrading to the PIC16C76/77. 1997 Microchip Technology Inc. PIC16C7X 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. TABLE 4-1: Address Name The special function registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature. PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 (1) 03h STATUS 04h(1) FSR 05h PORTA 06h PORTB 07h PORTC 08h 09h (4) IRP (4) RP1 RP0 TO PD Z DC C Indirect data memory address pointer -- -- 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu -- Unimplemented -- Unimplemented 0Ah(1,2) PCLATH -- 0Bh(1) INTCON 0Ch PIR1 Write Buffer for the upper 5 bits of the Program Counter -- -- -- -- -- -- GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u -- ADIF -- -- SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 Unimplemented ---0 0000 ---0 0000 0Dh -- 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx uuuu uuuu -- -- -- T1CKPS1 xxxx xxxx uuuu uuuu T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPM2 SSPM1 Timer2 module's register -- SSPOV CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 Unimplemented -- -- 19h -- Unimplemented -- -- 1Ah -- Unimplemented -- -- 1Bh -- Unimplemented -- -- 1Ch -- Unimplemented -- -- -- Unimplemented -- -- ADCON0 CCP1M3 xxxx xxxx uuuu uuuu SSPM0 -- 1Fh CCP1Y SSPM3 CCP1CON ADRES CCP1X CKP 17h 1Dh -- SSPEN 18h 1Eh -- --00 0000 --uu uuuu 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register WCOL -- xxxx xxxx uuuu uuuu A/D Result Register ADCS1 ADCS0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu CHS2 CHS1 CHS0 GO/DONE -- ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear. 1997 Microchip Technology Inc. DS30390E-page 23 PIC16C7X TABLE 4-1: Address Name PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (3) Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION 82h(1) PCL 83h(1) STATUS 84h(1) FSR 85h TRISA 86h TRISB 87h TRISC 88h -- Unimplemented -- Unimplemented 89h RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 TO -- 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer -- 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register --11 1111 --11 1111 PORTB Data Direction Register 1111 1111 1111 1111 PORTC Data Direction Register 1111 1111 1111 1111 8Ah(1,2) PCLATH -- 8Bh(1) INTCON 8Ch PIE1 Write Buffer for the upper 5 bits of the PC -- -- -- -- -- -- GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u -- ADIE -- -- SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 -- -- -- -- POR BOR ---- --qq ---- --uu ---0 0000 ---0 0000 8Dh -- 8Eh PCON 8Fh -- Unimplemented -- -- 90h -- Unimplemented -- -- -- Unimplemented -- -- 91h Unimplemented -- -- -- 92h PR2 Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT -- -- -- 1111 1111 1111 1111 D/A P 0000 0000 0000 0000 S R/W UA BF --00 0000 --00 0000 95h -- Unimplemented -- -- 96h -- Unimplemented -- -- 97h -- Unimplemented -- -- 98h -- Unimplemented -- -- 99h -- Unimplemented -- -- 9Ah -- Unimplemented -- -- 9Bh -- Unimplemented -- -- 9Ch -- Unimplemented -- -- 9Dh -- Unimplemented -- -- 9Eh -- Unimplemented -- -- ---- -000 ---- -000 9Fh ADCON1 -- -- -- -- -- PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear. DS30390E-page 24 1997 Microchip Technology Inc. PIC16C7X TABLE 4-2: Address Name PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 0 00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 (4) 03h STATUS 04h(4) FSR 05h PORTA 06h PORTB (7) (7) IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer -- -- 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu (5) 09h PORTE -- -- -- 0Ah(1,4) PCLATH -- -- -- 0Bh(4) INTCON 0Ch PIR1 0Dh PIR2 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON 18h RCSTA 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON 1Eh ADRES 1Fh ADCON0 -- -- RE2 RE1 RE0 Write Buffer for the upper 5 bits of the Program Counter ---- -xxx ---- -uuu ---0 0000 ---0 0000 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 -- -- -- - -- -- -- CCP2IF ---- ---0 ---- ---0 -- -- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPM2 SSPM1 Timer2 module's register -- 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV --00 0000 --uu uuuu SSPEN CKP SSPM3 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 -- -- CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 SPEN RX9 SREN CREN -- FERR OERR RX9D 0000 -00x 0000 -00x -- -- CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 A/D Result Register ADCS1 ADCS0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu CHS2 CHS1 CHS0 GO/DONE -- ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 4: These registers can be addressed from either bank. 5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as `0'. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear. 1997 Microchip Technology Inc. DS30390E-page 25 PIC16C7X TABLE 4-2: Address Name PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 1 80h(4) INDF 81h OPTION 82h(4) PCL (4) 83h STATUS 84h(4) FSR 85h TRISA 86h TRISB Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte (7) IRP (7) RP1 RP0 TO -- 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer -- 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register --11 1111 --11 1111 PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111 (5) 89h TRISE IBF OBF IBOV 8Ah(1,4) PCLATH -- -- -- 8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 -- -- -- -- -- -- -- CCP2IE ---- ---0 ---- ---0 8Eh PCON -- -- -- -- -- -- POR BOR(6) ---- --qq ---- --uu 8Fh -- Unimplemented -- -- 90h -- Unimplemented -- -- -- Unimplemented -- -- 91h PSPMODE -- PORTE Data Direction Bits 0000 -111 0000 -111 Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 92h PR2 Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT 95h -- Unimplemented -- -- 96h -- Unimplemented -- -- 97h -- Unimplemented -- -- 98h TXSTA 99h SPBRG -- CSRC -- TX9 1111 1111 1111 1111 D/A TXEN P SYNC 0000 0000 0000 0000 S -- R/W BRGH UA TRMT BF TX9D Baud Rate Generator Register --00 0000 --00 0000 0000 -010 0000 -010 0000 0000 0000 0000 9Ah -- Unimplemented -- -- 9Bh -- Unimplemented -- -- 9Ch -- Unimplemented -- -- 9Dh -- Unimplemented -- -- 9Eh -- Unimplemented -- -- ---- -000 ---- -000 9Fh ADCON1 -- -- -- -- -- PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 4: These registers can be addressed from either bank. 5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as `0'. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear. DS30390E-page 26 1997 Microchip Technology Inc. PIC16C7X TABLE 4-3: Address PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 0 00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 (4) 03h STATUS 04h(4) FSR 05h PORTA 06h PORTB IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer -- -- 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu (5) 09h PORTE -- -- -- 0Ah(1,4) PCLATH -- -- -- 0Bh(4) INTCON 0Ch PIR1 0Dh PIR2 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON 18h RCSTA 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON 1Eh ADRES 1Fh ADCON0 -- -- RE2 RE1 RE0 Write Buffer for the upper 5 bits of the Program Counter ---- -xxx ---- -uuu ---0 0000 ---0 0000 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 -- -- -- - -- -- -- CCP2IF -- -- xxxx xxxx uuuu uuuu T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPM2 SSPM1 Timer2 module's register -- SSPOV --00 0000 --uu uuuu 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register WCOL ---- ---0 ---- ---0 xxxx xxxx uuuu uuuu SSPEN CKP SSPM3 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 -- -- CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 SPEN RX9 SREN CREN -- FERR OERR RX9D 0000 -00x 0000 -00x -- -- CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 A/D Result Register ADCS1 ADCS0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu CHS2 CHS1 CHS0 GO/DONE -- ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and PORTE are not physically implemented on the PIC16C76, read as `0'. 1997 Microchip Technology Inc. DS30390E-page 27 PIC16C7X TABLE 4-3: Address PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 1 80h(4) INDF 81h OPTION 82h(4) PCL (4) 83h STATUS 84h(4) FSR 85h TRISA 86h TRISB Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO -- 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer -- 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register --11 1111 --11 1111 PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111 (5) 89h TRISE IBF OBF IBOV 8Ah(1,4) PCLATH -- -- -- 8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 -- -- -- -- -- -- -- CCP2IE ---- ---0 ---- ---0 8Eh PCON -- -- -- -- -- -- POR BOR ---- --qq ---- --uu 8Fh -- Unimplemented -- -- 90h -- Unimplemented -- -- -- Unimplemented -- -- 91h PSPMODE -- PORTE Data Direction Bits 0000 -111 0000 -111 Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 92h PR2 Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT 95h -- Unimplemented -- -- 96h -- Unimplemented -- -- Unimplemented -- -- 97h -- 98h TXSTA 99h SPBRG SMP CKE CSRC TX9 1111 1111 1111 1111 D/A TXEN P SYNC 0000 0000 0000 0000 S -- R/W BRGH UA BF TRMT TX9D Baud Rate Generator Register 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 9Ah -- Unimplemented -- -- 9Bh -- Unimplemented -- -- 9Ch -- Unimplemented -- -- 9Dh -- Unimplemented -- -- 9Eh -- Unimplemented -- -- ---- -000 ---- -000 9Fh ADCON1 -- -- -- -- -- PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and PORTE are not physically implemented on the PIC16C76, read as `0'. DS30390E-page 28 1997 Microchip Technology Inc. PIC16C7X TABLE 4-3: Address PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 2 100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 102h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 103h(4) STATUS 104h(4) FSR IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu 105h -- 106h PORTB 107h -- Unimplemented -- -- 108h -- Unimplemented -- -- -- Unimplemented -- -- 109h Unimplemented -- PORTB Data Latch when written: PORTB pins when read (1,4) PCLATH -- -- -- (4) INTCON GIE PEIE T0IE 10Ah 10Bh 10Ch10Fh -- Write Buffer for the upper 5 bits of the Program Counter INTE RBIE -- xxxx xxxx uuuu uuuu T0IF INTF ---0 0000 ---0 0000 RBIF Unimplemented 0000 000x 0000 000u -- -- Bank 3 180h(4) INDF 181h OPTION 182h(4) PCL 183h(4) STATUS 184h(4) FSR Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu 185h -- 186h TRISB 187h -- Unimplemented -- -- 188h -- Unimplemented -- -- -- Unimplemented -- -- 189h Unimplemented -- PORTB Data Direction Register (1,4) PCLATH -- -- -- (4) INTCON GIE PEIE T0IE 18Ah 18Bh 18Ch18Fh -- Unimplemented -- 1111 1111 1111 1111 Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF ---0 0000 ---0 0000 0000 000x 0000 000u -- -- Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and PORTE are not physically implemented on the PIC16C76, read as `0'. 1997 Microchip Technology Inc. DS30390E-page 29 PIC16C7X 4.2.2.1 STATUS REGISTER Applicable Devices 72 73 73A 74 74A 76 77 For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." The STATUS register, shown in Figure 4-7, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. FIGURE 4-7: R/W-0 IRP bit7 bit 7: Note 1: For those devices that do not use bits IRP and RP1 (STATUS<7:6>), maintain these bits clear to ensure upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. DS30390E-page 30 1997 Microchip Technology Inc. PIC16C7X 4.2.2.2 OPTION REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-8: R/W-1 RBPU bit7 To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. OPTION REGISTER (ADDRESS 81h, 181h) R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module R/W-1 PS0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1997 Microchip Technology Inc. DS30390E-page 31 PIC16C7X 4.2.2.3 INTCON REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. FIGURE 4-9: R/W-0 GIE bit7 Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7: GIE:(1) Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note 1: For the PIC16C73 and PIC16C74, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be unintentionally re-enabled by the RETFIE instruction in the user's Interrupt Service Routine. Refer to Section 14.5 for a detailed description. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30390E-page 32 1997 Microchip Technology Inc. PIC16C7X 4.2.2.4 PIE1 REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. This register contains the individual enable bits for the peripheral interrupts. FIGURE 4-10: PIE1 REGISTER PIC16C72 (ADDRESS 8Ch) U-0 -- bit7 R/W-0 ADIE U-0 -- U-0 -- R/W-0 SSPIE bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 1997 Microchip Technology Inc. DS30390E-page 33 PIC16C7X FIGURE 4-11: PIE1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 8Ch) R/W-0 PSPIE(1) bit7 R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt R/W-0 TMR1IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset Note 1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved on these devices, always maintain this bit clear. DS30390E-page 34 1997 Microchip Technology Inc. PIC16C7X 4.2.2.5 PIR1 REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: This register contains the individual flag bits for the Peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. FIGURE 4-12: PIR1 REGISTER PIC16C72 (ADDRESS 0Ch) U-0 -- bit7 R/W-0 ADIF U-0 -- U-0 -- R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit0 bit 7: Unimplemented: Read as '0' bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 1997 Microchip Technology Inc. DS30390E-page 35 PIC16C7X FIGURE 4-13: PIR1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 0Ch) R/W-0 PSPIF(1) bit7 R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7: PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved on these devices, always maintain this bit clear. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30390E-page 36 1997 Microchip Technology Inc. PIC16C7X 4.2.2.6 PIE2 REGISTER Applicable Devices 72 73 73A 74 74A 76 77 This register contains the individual enable bit for the CCP2 peripheral interrupt. FIGURE 4-14: PIE2 REGISTER (ADDRESS 8Dh) U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CCP2IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 1997 Microchip Technology Inc. DS30390E-page 37 PIC16C7X 4.2.2.7 PIR2 REGISTER Applicable Devices 72 73 73A 74 74A 76 77 . Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. U-0 -- R/W-0 CCP2IF bit0 This register contains the CCP2 interrupt flag bit. FIGURE 4-15: PIR2 REGISTER (ADDRESS 0Dh) U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30390E-page 38 1997 Microchip Technology Inc. PIC16C7X 4.2.2.8 PCON REGISTER Applicable Devices 72 73 73A 74 74A 76 77 Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word). FIGURE 4-16: PCON REGISTER (ADDRESS 8Eh) U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-q BOR(1) bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR(1): Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Brown-out Reset is not implemented on the PIC16C73/74. 1997 Microchip Technology Inc. DS30390E-page 39 PIC16C7X 4.3 PCL and PCLATH Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. Applicable Devices 72 73 73A 74 74A 76 77 The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-17 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). FIGURE 4-17: LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 PC 5 8 PCLATH<4:0> Instruction with PCL as Destination ALU PCLATH PCH 12 11 10 Program Memory Paging Applicable Devices 72 73 73A 74 74A 76 77 PIC16C7X devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack). Note: 0 7 GOTO, CALL PCLATH<4:3> 11 Opcode <10:0> PCLATH 4.3.1 4.4 PCL 8 PC 2 Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address. PIC16C7X devices with 4K or less of program memory ignore paging bit PCLATH<4>. The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products. COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556). 4.3.2 STACK The PIC16CXX family has an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS30390E-page 40 1997 Microchip Technology Inc. PIC16C7X Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used). 4.5 EXAMPLE 4-1: The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. ORG 0x500 BSF PCLATH,3 BCF PCLATH,4 CALL SUB1_P1 : : : ORG 0x900 SUB1_P1: : : RETURN Indirect Addressing, INDF and FSR Registers Applicable Devices 72 73 73A 74 74A 76 77 CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-18. ;Select page 1 (800h-FFFh) ;Only on >4K devices ;Call subroutine in ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2. ;return to Call subroutine ;in page 0 (000h-7FFh) EXAMPLE 4-2: movlw movwf clrf incf btfss goto NEXT INDIRECT ADDRESSING 0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next CONTINUE : ;yes continue FIGURE 4-18: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing from opcode RP1:RP0 6 bank select location select 0 IRP 7 bank select 00 00h 01 80h 10 100h FSR register 0 location select 11 180h not used Data Memory 7Fh Bank 0 FFh Bank 1 17Fh Bank 2 1FFh Bank 3 For register file map detail see Figure 4-4, and Figure 4-5. 1997 Microchip Technology Inc. DS30390E-page 41 PIC16C7X NOTES: DS30390E-page 42 1997 Microchip Technology Inc. PIC16C7X 5.0 I/O PORTS FIGURE 5-1: Applicable Devices 72 73 73A 74 74A 76 77 Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 Data bus BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS D Q VDD WR Port Q CK PORTA and TRISA Registers Data Latch Applicable Devices 72 73 73A 74 74A 76 77 D WR TRIS PORTA is a 6-bit latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'. TRIS Latch Q RD PORT To A/D Converter Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 5-2: Data bus EXAMPLE 5-1: WR TRIS STATUS, RP0 STATUS, RP1 PORTA BSF MOVLW STATUS, RP0 0xCF MOVWF TRISA ; ; ; ; ; ; ; ; ; ; ; ; ; PIC16C76/77 only Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6> are always read as '0'. D EN WR PORT BCF BCF CLRF TTL input buffer RD TRIS The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. INITIALIZING PORTA I/O pin(1) VSS Analog input mode Q Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin(s). Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. N Q CK The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input. P BLOCK DIAGRAM OF RA4/ T0CKI PIN D Q CK Q N I/O pin(1) Data Latch D Q CK Q VSS Schmitt Trigger input buffer TRIS Latch RD TRIS Q D EN EN RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only. 1997 Microchip Technology Inc. DS30390E-page 43 PIC16C7X TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI bit0 bit1 bit2 bit3 bit4 TTL TTL TTL TTL ST Function Input/output or analog input Input/output or analog input Input/output or analog input Input/output or analog input or VREF Input/output or external clock input for Timer0 Output is open drain type RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address Name Bit 7 Bit 6 05h PORTA -- -- 85h TRISA -- -- 9Fh ADCON1 -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 ---- -000 ---- -000 PORTA Data Direction Register -- -- -- PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS30390E-page 44 1997 Microchip Technology Inc. PIC16C7X 5.2 PORTB and TRISB Registers Applicable Devices 72 73 73A 74 74A 76 77 PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). EXAMPLE 5-2: INITIALIZING PORTB BCF CLRF STATUS, RP0 PORTB BSF MOVLW STATUS, RP0 0xCF MOVWF TRISB ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. FIGURE 5-3: BLOCK DIAGRAM OF RB3:RB0 PINS VDD RBPU(2) Data bus WR Port weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRIS Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552). Note: For the PIC16C73/74, if a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then interrupt flag bit RBIF may not get set. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. TTL Input Buffer CK RD TRIS Q RD Port D EN RB0/INT Schmitt Trigger Buffer RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). 1997 Microchip Technology Inc. DS30390E-page 45 PIC16C7X FIGURE 5-4: BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C73/74) FIGURE 5-5: VDD RBPU(2) weak P pull-up Data Latch D Q Data bus WR Port I/O pin(1) CK WR TRIS VDD RBPU(2) Data bus WR Port TRIS Latch D Q TTL Input Buffer CK RD TRIS Q BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C72/ 73A/74A/76/77) weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q ST Buffer WR TRIS Latch D TTL Input Buffer CK RD TRIS Q ST Buffer Latch D EN RD Port Set RBIF EN RD Port Q1 Set RBIF From other RB7:RB4 pins Q D EN RD Port From other RB7:RB4 pins Q RD Port EN RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). TABLE 5-3: Name D Q3 RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). PORTB FUNCTIONS Bit# Buffer Function TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. RB0/INT bit0 DS30390E-page 46 1997 Microchip Technology Inc. PIC16C7X TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB 1111 1111 1111 1111 81h, 181h OPTION 1111 1111 1111 1111 PORTB Data Direction Register RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. 1997 Microchip Technology Inc. DS30390E-page 47 PIC16C7X 5.3 PORTC and TRISC Registers FIGURE 5-6: Applicable Devices 72 73 73A 74 74A 76 77 PORTC is an 8-bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. EXAMPLE 5-3: PORT/PERIPHERAL Select(2) Peripheral Data Out Data bus WR PORT D STATUS, RP0 STATUS, RP1 PORTC BSF MOVLW STATUS, RP0 0xCF MOVWF TRISC ; ; ; ; ; ; ; ; ; ; ; ; Select Bank 0 PIC16C76/77 only Initialize PORTC by clearing output data latches Select Bank 1 Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs VDD 0 Q P 1 CK Q Data Latch WR TRIS D CK I/O pin(1) Q Q N TRIS Latch VSS Schmitt Trigger RD TRIS Peripheral OE(3) Q INITIALIZING PORTC BCF BCF CLRF TABLE 5-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) D EN RD PORT Peripheral input Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input RC1/T1OSI/CCP2(1) bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output (2) RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART Synchronous Clock RC7/RX/DT(2) bit7 ST Input/output port pin or USART Asynchronous Receive, or USART Synchronous Data Legend: ST = Schmitt Trigger input Note 1: The CCP2 multiplexed function is not enabled on the PIC16C72. 2: The TX/CK and RX/DT multiplexed functions are not enabled on the PIC16C72. DS30390E-page 48 1997 Microchip Technology Inc. PIC16C7X TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC 1111 1111 1111 1111 PORTC Data Direction Register Legend: x = unknown, u = unchanged. 1997 Microchip Technology Inc. DS30390E-page 49 PIC16C7X 5.4 PORTD and TRISD Registers FIGURE 5-7: Applicable Devices 72 73 73A 74 74A 76 77 Data bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. D WR PORT PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. PORTD BLOCK DIAGRAM (IN I/O PORT MODE) Q I/O pin(1) CK Data Latch D WR TRIS Q Schmitt Trigger input buffer CK TRIS Latch RD TRIS Q D EN EN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 5-7: Name PORTD FUNCTIONS Bit# Buffer Type bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0 RD1/PSP1 bit1 (1) ST/TTL Input/output port pin or parallel slave port bit1 RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2 bit3 (1) Input/output port pin or parallel slave port bit3 (1) Input/output port pin or parallel slave port bit4 (1) RD0/PSP0 RD3/PSP3 RD4/PSP4 ST/TTL bit4 ST/TTL Function RD5/PSP5 bit5 ST/TTL Input/output port pin or parallel slave port bit5 RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6 (1) Input/output port pin or parallel slave port bit7 RD7/PSP7 bit7 ST/TTL Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode. TABLE 5-8: Address Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 08h PORTD RD7 88h TRISD PORTD Data Direction Register 89h TRISE IBF RD6 OBF IBOV PSPMODE -- PORTE Data Direction Bits Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD. DS30390E-page 50 1997 Microchip Technology Inc. PIC16C7X 5.5 PORTE and TRISE Register Note: Applicable Devices 72 73 73A 74 74A 76 77 On a Power-on Reset these pins are configured as analog inputs. FIGURE 5-8: PORTE has three pins RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. Data bus D WR PORT I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs) and that register ADCON1 is configured for digital I/O. In this mode the input buffers are TTL. I/O pin(1) CK D WR TRIS Q Schmitt Trigger input buffer CK TRIS Latch PORTE pins are multiplexed with analog inputs. The operation of these pins is selected by control bits in the ADCON1 register. When selected as an analog input, these pins will read as '0's. RD TRIS Q TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. R-0 IBF bit7 Q Data Latch Figure 5-9 shows the TRISE register, which also controls the parallel slave port operation. FIGURE 5-9: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) D EN EN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. TRISE REGISTER (ADDRESS 89h) R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 bit2 R/W-1 bit1 R/W-1 bit0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7 : IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6: OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4: PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel slave port mode 0 = General purpose I/O mode bit 3: Unimplemented: Read as '0' PORTE Data Direction Bits bit 2: Bit2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output bit 1: Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0: Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output 1997 Microchip Technology Inc. DS30390E-page 51 PIC16C7X TABLE 5-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in parallel slave port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected) RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in parallel slave port mode or analog input: WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected) bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port mode or analog input: CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode. RE2/CS/AN7 TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets PORTE -- -- -- -- -- RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE -- 0000 -111 0000 -111 9Fh ADCON1 -- -- -- -- -- ---- -000 ---- -000 Address Name 09h PORTE Data Direction Bits PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE. DS30390E-page 52 1997 Microchip Technology Inc. PIC16C7X 5.6 I/O Programming Considerations EXAMPLE 5-4: Applicable Devices 72 73 73A 74 74A 76 77 5.6.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched to an output, the content of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-4 shows the effect of two sequential readmodify-write instructions on an I/O port. READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT ;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high). A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip. 5.6.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 510). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/ O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-10: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched PC PC + 1 MOVWF PORTB MOVF PORTB,W write to PORTB PC + 2 PC + 3 NOP NOP This example shows a write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD) RB7:RB0 where TCY = instruction cycle TPD = propagation delay Port pin sampled here TPD Instruction executed NOP MOVWF PORTB write to PORTB 1997 Microchip Technology Inc. Note: MOVF PORTB,W Therefore, at higher clock frequencies, a write followed by a read may be problematic. DS30390E-page 53 PIC16C7X 5.7 Parallel Slave Port Applicable Devices 72 73 73A 74 74A 76 77 PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode it is asynchronously readable and writable by the external world through RD control input pin RE0/RD/AN5 and WR control input pin RE1/WR/AN6. It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD/AN5 to be the RD input, RE1/ WR/AN6 to be the WR input and RE2/CS/AN7 to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set) and the A/D port configuration bits PCFG2:PCFG0 (ADCON1<2:0>) must be set, which will configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches, one for data-out (from the PIC16/17) and one for data input. The user writes 8-bit data to PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored, since the microprocessor is controlling the direction of data flow. A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR lines become high (level triggered), then the Input Buffer Full status flag bit IBF (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure 5-12). The interrupt flag bit PSPIF (PIR1<7>) is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The input Buffer Overflow status flag bit IBOV (TRISE<5>) is set if a second write to the Parallel Slave Port is attempted when the previous byte has not been read out of the buffer. FIGURE 5-11: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data bus D WR PORT Q RDx pin CK TTL Q RD PORT D EN EN One bit of PORTD Set interrupt flag PSPIF (PIR1<7>) Read TTL RD Chip Select TTL CS TTL WR Write Note: I/O pin has protection diodes to VDD and VSS. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full status flag bit OBF (TRISE<6>) is cleared immediately (Figure 5-13) indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in Parallel Slave Port mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>). DS30390E-page 54 1997 Microchip Technology Inc. PIC16C7X FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Address Name Bit 7 Bit 6 08h PORTD 09h PORTE -- -- 89h TRISE IBF OBF Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port data latch when written: Port pins when read -- -- IBOV PSPMODE -- -- RE2 RE1 RE0 PORTE Data Direction Bits Value on: POR, BOR Value on all other resets xxxx xxxx uuuu uuuu ---- -xxx ---- -uuu 0000 -111 0000 -111 0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1 -- -- PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 -- -- -- Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. 1997 Microchip Technology Inc. DS30390E-page 55 PIC16C7X NOTES: DS30390E-page 56 1997 Microchip Technology Inc. PIC16C7X 6.0 OVERVIEW OF TIMER MODULES Applicable Devices 72 73 73A 74 74A 76 77 CCP module, Timer1 is the time-base for 16-bit Capture or the 16-bit Compare and must be synchronized to the device. 6.3 Applicable Devices 72 73 73A 74 74A 76 77 The PIC16C72, PIC16C73/73A, PIC16C74/74A, PIC16C76/77 each have three timer modules. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer overflow). Each of these modules is explained in full detail in the following sections. The timer modules are: * Timer0 Module (Section 7.0) * Timer1 Module (Section 8.0) * Timer2 Module (Section 9.0) 6.1 Timer0 Overview Applicable Devices 72 73 73A 74 74A 76 77 The Timer0 module is a simple 8-bit overflow counter. The clock source can be either the internal system clock (Fosc/4) or an external clock. When the clock source is an external clock, the Timer0 module can be selected to increment on either the rising or falling edge. The Timer0 module also has a programmable prescaler option. This prescaler can be assigned to either the Timer0 module or the Watchdog Timer. Bit PSA (OPTION<3>) assigns the prescaler, and bits PS2:PS0 (OPTION<2:0>) determine the prescaler value. Timer0 can increment at the following rates: 1:1 (when prescaler assigned to Watchdog timer), 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, and 1:256 (Timer0 only). Synchronization of the external clock occurs after the prescaler. When the prescaler is used, the external clock frequency may be higher then the device's frequency. The maximum frequency is 50 MHz, given the high and low time requirements of the clock. 6.2 Timer1 Overview Applicable Devices 72 73 73A 74 74A 76 77 Timer1 is a 16-bit timer/counter. The clock source can be either the internal system clock (Fosc/4), an external clock, or an external crystal. Timer1 can operate as either a timer or a counter. When operating as a counter (external clock source), the counter can either operate synchronized to the device or asynchronously to the device. Asynchronous operation allows Timer1 to operate during sleep, which is useful for applications that require a real-time clock as well as the power savings of SLEEP mode. Timer2 Overview Timer2 is an 8-bit timer with a programmable prescaler and postscaler, as well as an 8-bit period register (PR2). Timer2 can be used with the CCP1 module (in PWM mode) as well as the Baud Rate Generator for the Synchronous Serial Port (SSP). The prescaler option allows Timer2 to increment at the following rates: 1:1, 1:4, 1:16. The postscaler allows the TMR2 register to match the period register (PR2) a programmable number of times before generating an interrupt. The postscaler can be programmed from 1:1 to 1:16 (inclusive). 6.4 CCP Overview Applicable Devices 72 73 73A 74 74A 76 77 The CCP module(s) can operate in one of these three modes: 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM). Capture mode captures the 16-bit value of TMR1 into the CCPRxH:CCPRxL register pair. The capture event can be programmed for either the falling edge, rising edge, fourth rising edge, or the sixteenth rising edge of the CCPx pin. Compare mode compares the TMR1H:TMR1L register pair to the CCPRxH:CCPRxL register pair. When a match occurs an interrupt can be generated, and the output pin CCPx can be forced to given state (High or Low), TMR1 can be reset (CCP1), or TMR1 reset and start A/D conversion (CCP2). This depends on the control bits CCPxM3:CCPxM0. PWM mode compares the TMR2 register to a 10-bit duty cycle register (CCPRxH:CCPRxL<5:4>) as well as to an 8-bit period register (PR2). When the TMR2 register = Duty Cycle register, the CCPx pin will be forced low. When TMR2 = PR2, TMR2 is cleared to 00h, an interrupt can be generated, and the CCPx pin (if an output) will be forced high. Timer1 also has a prescaler option which allows Timer1 to increment at the following rates: 1:1, 1:2, 1:4, and 1:8. Timer1 can be used in conjunction with the Capture/Compare/PWM module. When used with a 1997 Microchip Technology Inc. DS30390E-page 57 PIC16C7X NOTES: DS30390E-page 58 1997 Microchip Technology Inc. PIC16C7X 7.0 TIMER0 MODULE Source Edge Select bit T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. Applicable Devices 72 73 73A 74 74A 76 77 The Timer0 module timer/counter has the following features: * * * * * * The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler. 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Figure 7-1 is a simplified block diagram of the Timer0 module. 7.1 Applicable Devices 72 73 73A 74 74A 76 77 Timer mode is selected by clearing bit T0CS (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register. The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. See Figure 7-4 for Timer0 interrupt timing. Counter mode is selected by setting bit T0CS (OPTION<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 FIGURE 7-1: Timer0 Interrupt TIMER0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 1 Sync with Internal clocks 1 Programmable Prescaler RA4/T0CKI pin 8 0 TMR0 PSout (2 cycle delay) T0SE 3 Set interrupt flag bit T0IF on overflow PSA PS2, PS1, PS0 T0CS Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram). FIGURE 7-2: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 Instruction Fetch TMR0 T0 PC PC+1 MOVWF TMR0 MOVF TMR0,W T0+1 Instruction Executed 1997 Microchip Technology Inc. PC+2 PC+3 MOVF TMR0,W MOVF TMR0,W T0+2 NT0 NT0 Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 PC+4 MOVF TMR0,W NT0 Read TMR0 reads NT0 PC+5 PC+6 MOVF TMR0,W NT0+1 Read TMR0 reads NT0 + 1 NT0+2 T0 Read TMR0 reads NT0 + 2 DS30390E-page 59 PIC16C7X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch PC PC+1 MOVWF TMR0 MOVF TMR0,W PC+3 Instruction Execute PC+5 MOVF TMR0,W PC+6 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 PC+6 NT0+1 NT0 Write TMR0 executed FIGURE 7-4: PC+4 MOVF TMR0,W T0+1 T0 TMR0 PC+2 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 TIMER0 INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) Timer0 FEh T0IF bit (INTCON<2>) FFh 00h 01h 02h 1 1 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction fetched Inst (PC) Instruction executed Inst (PC-1) PC +1 PC +1 Inst (PC+1) Inst (PC) Dummy cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy cycle Inst (0004h) Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. DS30390E-page 60 1997 Microchip Technology Inc. PIC16C7X 7.2 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. Applicable Devices 72 73 73A 74 74A 76 77 When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. FIGURE 7-5: 7.2.2 TMR0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-5 shows the delay from the external clock edge to the timer incrementing. TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Prescaler output (2) Q1 Q2 Q3 Q4 Small pulse misses sampling (1) (3) External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 1997 Microchip Technology Inc. DS30390E-page 61 PIC16C7X 7.3 Prescaler The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. Applicable Devices 72 73 73A 74 74A 76 77 When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. FIGURE 7-6: Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus CLKOUT (=Fosc/4) 0 RA4/T0CKI pin 8 M U X 1 M U X 0 1 SYNC 2 Cycles TMR0 reg T0SE T0CS 0 Watchdog Timer 1 M U X Set flag bit T0IF on Overflow PSA 8-bit Prescaler 8 8 - to - 1MUX PS2:PS0 PSA WDT Enable bit 1 0 MUX PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>). DS30390E-page 62 1997 Microchip Technology Inc. PIC16C7X 7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. EXAMPLE 7-1: CHANGING PRESCALER (TIMER0WDT) Lines 2 and 3 do NOT have to be included if the final desired prescale value is other than 1:1. If 1:1 is final desired value, then a temporary prescale value is set in lines 2 and 3 and the final prescale value will be set in lines 10 and 11. 1) BSF STATUS, RP0 ;Bank 1 2) MOVLW b'xx0x0xxx' ;Select clock source and prescale value of 3) MOVWF OPTION_REG ;other than 1:1 4) BCF STATUS, RP0 ;Bank 0 5) CLRF TMR0 ;Clear TMR0 and prescaler 6) BSF STATUS, RP1 ;Bank 1 7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value 8) MOVWF OPTION_REG ; 9) CLRWDT ;Clears WDT and prescaler 10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT 11) MOVWF OPTION_REG ; 12) BCF STATUS, RP0 ;Bank 0 To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 7-2. EXAMPLE 7-2: CLRWDT BSF MOVLW MOVWF BCF CHANGING PRESCALER (WDTTIMER0) STATUS, RP0 b'xxxx0xxx' OPTION_REG STATUS, RP0 TABLE 7-1: ;Clear WDT and prescaler ;Bank 1 ;Select TMR0, new prescale value and ;clock source ;Bank 0 REGISTERS ASSOCIATED WITH TIMER0 Address Name 01h,101h TMR0 0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h OPTION 85h TRISA Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR xxxx xxxx uuuu uuuu T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 --11 1111 --11 1111 Bit 5 Timer0 module's register GIE PEIE RBPU INTEDG -- -- PORTA Data Direction Register Value on all other resets Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. 1997 Microchip Technology Inc. DS30390E-page 63 PIC16C7X NOTES: DS30390E-page 64 1997 Microchip Technology Inc. PIC16C7X 8.0 TIMER1 MODULE In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. Applicable Devices 72 73 73A 74 74A 76 77 The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>). Timer1 can operate in one of two modes: * As a timer * As a counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). FIGURE 8-1: Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Timer1 also has an internal "reset input". This reset can be generated by either of the two CCP modules (Section 10.0). Figure 8-1 shows the Timer1 control register. For the PIC16C72/73A/74A/76/77, when the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/ T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. For the PIC16C73/74, when the Timer1 oscillator is enabled (T1OSCEN is set), RC1/T1OSI/CCP2 pin becomes an input, however the RC0/T1OSO/T1CKI pin will have to be configured as an input by setting the TRISC<0> bit. T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 -- -- R/W-0 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC bit7 R/W-0 R/W-0 TMR1CS TMR1ON bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1997 Microchip Technology Inc. DS30390E-page 65 PIC16C7X 8.1 Timer1 Operation in Timer Mode 8.2.1 Applicable Devices 72 73 73A 74 74A 76 77 When an external clock input is used for Timer1 in synchronized counter mode, it must meet certain requirements. The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of TMR1 after synchronization. Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. 8.2 When the prescaler is 1:1, the external clock input is the same as the prescaler output. The synchronization of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T1CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the appropriate electrical specifications, parameters 45, 46, and 47. Timer1 Operation in Synchronized Counter Mode Applicable Devices 72 73 73A 74 74A 76 77 Counter mode is selected by setting bit TMR1CS. In this mode the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set or pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared. When a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous ripplecounter type prescaler so that the prescaler output is symmetrical. In order for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T1CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T1CKI high and low time is that they do not violate the minimum pulse width requirements of 10 ns). Refer to the appropriate electrical specifications, parameters 40, 42, 45, 46, and 47. If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple-counter. In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. The prescaler however will continue to increment. FIGURE 8-2: EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow 0 TMR1 TMR1H Synchronized clock input TMR1L 1 TMR1ON on/off T1OSC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(2) T1SYNC (3) 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Prescaler 1, 2, 4, 8 Synchronize det 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2: The CCP2 module is not implemented in the PIC16C72. 3: For the PIC16C73 and PIC16C74, the Schmitt Trigger is not implemented in external clock mode. DS30390E-page 66 1997 Microchip Technology Inc. PIC16C7X 8.3 Timer1 Operation in Asynchronous Counter Mode Applicable Devices 72 73 73A 74 74A 76 77 If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 8.3.2). In asynchronous counter mode, Timer1 can not be used as a time-base for capture or compare operations. 8.3.1 EXTERNAL CLOCK INPUT TIMING WITH UNSYNCHRONIZED CLOCK If control bit T1SYNC is set, the timer will increment completely asynchronously. The input clock must meet certain minimum high time and low time requirements. Refer to the appropriate Electrical Specifications Section, timing parameters 45, 46, and 47. 8.3.2 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running, from an external asynchronous clock, will guarantee a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Example 8-1 is an example routine to read the 16-bit timer value. This is useful if the timer cannot be stopped. EXAMPLE 8-1: READING A 16-BIT FREERUNNING TIMER ; All interrupts MOVF TMR1H, MOVWF TMPH MOVF TMR1L, MOVWF TMPL MOVF TMR1H, SUBWF TMPH, BTFSC GOTO are disabled W ;Read high byte ; W ;Read low byte ; W ;Read high byte W ;Sub 1st read ; with 2nd read STATUS,Z ;Is result = 0 CONTINUE ;Good 16-bit read ; ; TMR1L may have rolled over between the read ; of the high and low bytes. Reading the high ; and low bytes now will read a good value. ; MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; ; Re-enable the Interrupt (if required) CONTINUE ;Continue with your code 8.4 Timer1 Oscillator Applicable Devices 72 73 73A 74 74A 76 77 A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 8-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. TABLE 8-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq C1 C2 LP 32 kHz 100 kHz 200 kHz 33 pF 15 pF 15 pF 33 pF 15 pF 15 pF These values are for design guidance only. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A 20 PPM 100 kHz Epson C-2 100.00 KC-P 20 PPM 200 kHz STD XTL 200.000 kHz 20 PPM Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 1997 Microchip Technology Inc. DS30390E-page 67 PIC16C7X 8.5 Resetting Timer1 using a CCP Trigger Output 8.6 Applicable Devices 72 73 73A 74 74A 76 77 Applicable Devices 72 73 73A 74 74A 76 77 The CCP2 module is not implemented on the PIC16C72 device. If the CCP1 or CCP2 module is configured in compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. Note: Resetting of Timer1 Register Pair (TMR1H, TMR1L) The special event triggers from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>). Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work. TMR1H and TMR1L registers are not reset to 00h on a POR or any other reset except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other resets, the register is unaffected. 8.7 Timer1 Prescaler Applicable Devices 72 73 73A 74 74A 76 77 The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL registers pair effectively becomes the period register for Timer1. TABLE 8-2: Address REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name 0Bh,8Bh, INTCON 10Bh,18Bh Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1,2) RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON 0Ch -- ADIE -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'. DS30390E-page 68 1997 Microchip Technology Inc. PIC16C7X 9.0 TIMER2 MODULE 9.1 Applicable Devices 72 73 73A 74 74A 76 77 Applicable Devices 72 73 73A 74 74A 76 77 Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR2 register * a write to the T2CON register * any device reset (Power-on Reset, MCLR reset, Watchdog Timer reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. 9.2 Output of TMR2 Applicable Devices 72 73 73A 74 74A 76 77 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock. FIGURE 9-1: Sets flag bit TMR2IF TIMER2 BLOCK DIAGRAM TMR2 output (1) Reset Figure 9-2 shows the Timer2 control register. Postscaler 1:1 to 1:16 4 EQ TMR2 reg Comparator Prescaler 1:1, 1:4, 1:16 FOSC/4 2 PR2 reg Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. 1997 Microchip Technology Inc. DS30390E-page 69 PIC16C7X FIGURE 9-2: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 -- bit7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit0 bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 TABLE 9-1: Address Name R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1,2) PSPIE ADIE (2) (2) TMR1IE 0000 0000 0000 0000 11h TMR2 Timer2 module's register 0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 12h T2CON 92h PR2 Legend: Note 1: 2: -- RCIE TXIE SSPIE CCP1IE TMR2IE TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 Timer2 Period Register 0000 000x 0000 000u 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'. DS30390E-page 70 1997 Microchip Technology Inc. PIC16C7X 10.0 CAPTURE/COMPARE/PWM MODULE(s) Applicable Devices 72 73 73A 74 74A 76 77 CCP1 72 73 73A 74 74A 76 77 CCP2 Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Both the CCP1 and CCP2 modules are identical in operation, with the exception of the operation of the special event trigger. Table 10-1 and Table 10-2 show the resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module is described with respect to CCP1. CCP2 operates the same as CCP1, except where noted. TABLE 10-2: CCP1 module: Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. CCP2 module: Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. For use of the CCP modules, refer to the Embedded Control Handbook, "Using the CCP Modules" (AN594). TABLE 10-1: CCP MODE - TIMER RESOURCE CCP Mode Timer Resource Capture Compare PWM Timer1 Timer1 Timer2 INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time-base. Capture Compare The compare should be configured for the special event trigger, which clears TMR1. Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1. PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt). PWM Capture None PWM Compare None 1997 Microchip Technology Inc. DS30390E-page 71 PIC16C7X FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h)/CCP2CON REGISTER (ADDRESS 1Dh) U-0 -- bit7 U-0 -- R/W-0 CCPxX R/W-0 R/W-0 CCPxY CCPxM3 R/W-0 CCPxM2 R/W-0 R/W-0 CCPxM1 CCPxM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCPxX:CCPxY: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode 10.1 Capture Mode Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 10-2: CAPTURE MODE OPERATION BLOCK DIAGRAM In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. 10.1.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition. DS30390E-page 72 Prescaler / 1, 4, 16 Set flag bit CCP1IF (PIR1<2>) RC2/CCP1 Pin CCPR1H CCPR1L Capture Enable and edge detect TMR1H TMR1L CCP1CON<3:0> Q's 10.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. 10.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode. 1997 Microchip Technology Inc. PIC16C7X 10.1.4 CCP PRESCALER 10.2.1 There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. Example 10-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. EXAMPLE 10-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW MOVWF 10.2 CCP1CON NEW_CAPT_PS CCP1CON ;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: 10.2.2 Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch. TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 10.2.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). 10.2.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. Compare Mode Applicable Devices 72 73 73A 74 74A 76 77 In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: * Driven High * Driven Low * Remains Unchanged The special trigger output of CCP2 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled). For the PIC16C72 only, the special event trigger output of CCP1 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled). The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. Note: The special event trigger from the CCP1and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>). FIGURE 10-3: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP1 only for PIC16C72, CCP2 only for PIC16C73/73A/74/74A/76/77). Special Event Trigger Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S Output Logic match RC2/CCP1 R Pin TRISC<2> Output Enable CCP1CON<3:0> Mode Select 1997 Microchip Technology Inc. Comparator TMR1H TMR1L DS30390E-page 73 PIC16C7X 10.3 PWM Mode 10.3.1 Applicable Devices 72 73 73A 74 74A 76 77 In Pulse Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 10-4 shows a simplified block diagram of the CCP module in PWM mode. For a step by step procedure on how to set up the CCP module for PWM operation, see Section 10.3.3. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: FIGURE 10-4: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty cycle registers CCPR1L 10.3.2 CCPR1H (Slave) R Comparator Q RC2/CCP1 TMR2 (Note 1) TRISC<2> Clear Timer, CCP1 pin and latch D.C. PR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base. A PWM output (Figure 10-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 10-5: PWM OUTPUT The Timer2 postscaler (see Section 9.1) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * Tosc * (TMR2 prescale value) S Comparator PWM PERIOD CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency: Period ( log = FOSC FPWM ) bits log(2) Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared. TMR2 = PR2 DS30390E-page 74 1997 Microchip Technology Inc. PIC16C7X EXAMPLE 10-2: PWM PERIOD AND DUTY CYCLE CALCULATION In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased. Desired PWM frequency is 78.125 kHz, Fosc = 20 MHz TMR2 prescale = 1 Table 10-3 lists example PWM frequencies and resolutions for Fosc = 20 MHz. The TMR2 prescaler and PR2 values are also shown. 1/78.125 kHz= [(PR2) + 1] * 4 * 1/20 MHz * 1 12.8 s = [(PR2) + 1] * 4 * 50 ns * 1 10.3.3 PR2 = 63 The following steps should be taken when configuring the CCP module for PWM operation: Find the maximum resolution of the duty cycle that can be used with a 78.125 kHz frequency and 20 MHz oscillator: 1. 1/78.125 kHz= 2PWM RESOLUTION * 1/20 MHz * 1 12.8 s =2 256 = 2PWM RESOLUTION PWM RESOLUTION 2. * 50 ns * 1 3. log(256) = (PWM Resolution) * log(2) 8.0 4. = PWM Resolution 5. At most, an 8-bit resolution duty cycle can be obtained from a 78.125 kHz frequency and a 20 MHz oscillator, i.e., 0 CCPR1L:CCP1CON<5:4> 255. Any value greater than 255 will result in a 100% duty cycle. TABLE 10-3: PWM Frequency Address Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz 1.22 kHz 4.88 kHz 19.53 kHz Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 10-4: SET-UP FOR PWM OPERATION 16 0xFF 10 4 0xFF 10 78.12 kHz 156.3 kHz 208.3 kHz 1 0x3F 8 1 0x1F 7 1 0x17 5.5 1 0xFF 10 REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Name 0Bh,8Bh, INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF PSPIF(1,2) ADIF Value on: POR, BOR Value on all other resets 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 0Ch PIR1 0Dh(2) PIR2 8Ch PIE1 8Dh(2) PIE2 87h TRISC 0Eh 0Fh 10h T1CON 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu -- -- PSPIE(1,2) ADIE -- -- -- -- -- -- -- CCP2IF ---- ---0 ---- ---0 RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 -- -- -- -- -- CCP2IE ---- ---0 ---- ---0 PORTC Data Direction Register 1111 1111 1111 1111 TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 17h CCP1CON 1Bh(2) CCPR2L Capture/Compare/PWM register2 (LSB) 1Ch(2) CCPR2H Capture/Compare/PWM register2 (MSB) 1Dh(2) CCP2CON -- -- -- -- CCP1X CCP2X CCP1Y CCP2Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'. 1997 Microchip Technology Inc. DS30390E-page 75 PIC16C7X TABLE 10-5: Address REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name 0Bh,8Bh, INTCON 10Bh,18Bh 0Ch PIR1 Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh(2) PIR2 -- -- -- -- -- -- -- CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh(2) PIE2 -- -- -- -- -- -- -- CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 module's register 0000 0000 0000 0000 92h PR2 Timer2 module's period register 1111 1111 1111 1111 12h T2CON 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON 1Bh(2) CCPR2L Capture/Compare/PWM register2 (LSB) 1Ch(2) CCPR2H Capture/Compare/PWM register2 (MSB) 1Dh(2) CCP2CON Legend: Note 1: 2: -- -- -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 -- -- CCP1X CCP2X CCP1Y CCP2Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'. DS30390E-page 76 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 11.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE 11.1 SSP Module Overview PIC16C7X The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) The SSP module in I2C mode works the same in all PIC16C7X devices that have an SSP module. However the SSP Module in SPI mode has differences between the PIC16C76/77 and the other PIC16C7X devices. The register definitions and operational description of SPI mode has been split into two sections because of the differences between the PIC16C76/77 and the other PIC16C7X devices. The default reset values of both the SPI modules is the same regardless of the device: 11.2 SPI Mode for PIC16C72/73/73A/74/74A ..........78 11.3 SPI Mode for PIC16C76/77..............................83 11.4 I2CTM Overview ................................................89 11.5 SSP I2C Operation...........................................93 Refer to Application Note AN578, "Use of the SSP Module in the I 2C Multi-Master Environment." 1997 Microchip Technology Inc. DS30390E-page 77 Applicable Devices PIC16C7X 11.2 72 73 73A 74 74A 76 77 SPI Mode for PIC16C72/73/73A/74/74A This section contains register definitions and operational characteristics of the SPI module for the PIC16C72, PIC16C73, PIC16C73A, PIC16C74, PIC16C74A. FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) U-0 -- bit7 U-0 -- R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS30390E-page 78 1997 Microchip Technology Inc. Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 WCOL bit7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Detect bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR register is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge. 0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge. In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master mode, clock = Fosc/4 0001 = SPI master mode, clock = Fosc/16 0010 = SPI master mode, clock = Fosc/64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled Master Mode (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled 1997 Microchip Technology Inc. DS30390E-page 79 PIC16C7X 11.2.1 Applicable Devices 72 73 73A 74 74A 76 77 OPERATION OF SSP MODULE IN SPI MODE Applicable Devices 72 73 73A 74 74A 76 77 The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) Additionally a fourth pin may be used when in a slave mode of operation: * Slave Select (SS) When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>). These control bits allow the following to be specified: * Master Mode (SCK is the clock output) * Slave Mode (SCK is the clock input) * Clock Polarity (Output/Input data on the Rising/ Falling edge of SCK) * Clock Rate (Master mode only) * Slave Select Mode (Slave mode only) The SSP consists of a transmit/receive Shift Register (SSPSR) and a Buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8-bits of data have been received, that byte is moved to the SSPBUF register. Then the Buffer Full bit, BF (SSPSTAT<0>) and flag bit SSPIF are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit, WCOL (SSPCON<7>) will be set. User software must clear bit WCOL so that it can be determined if the following write(s) to the SSPBUF completed successfully. When the application software is expecting to receive valid data, the SSPBUF register should be read before the next byte of data to transfer is written to the SSPBUF register. The Buffer Full bit BF (SSPSTAT<0>) indicates when the SSPBUF register has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally the SSP Interrupt is used to determine when the transmission/reception has completed. The SSPBUF register must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 11-1 shows the loading of the SSPBUF (SSPSR) register for data transmission. The shaded instruction is only required if the received data is meaningful. DS30390E-page 80 EXAMPLE 11-1: LOADING THE SSPBUF (SSPSR) REGISTER BSF STATUS, RP0 LOOP BTFSS SSPSTAT, BF GOTO BCF MOVF ;Specify Bank 1 ;Has data been ;received ;(transmit ;complete)? ;No ;Specify Bank 0 ;W reg = contents ;of SSPBUF ;Save in user RAM ;W reg = contents ; of TXDATA ;New data to xmit LOOP STATUS, RP0 SSPBUF, W MOVWF RXDATA MOVF TXDATA, W MOVWF SSPBUF The block diagram of the SSP module, when in SPI mode (Figure 11-3), shows that the SSPSR register is not directly readable or writable, and can only be accessed from addressing the SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various status conditions. FIGURE 11-3: SSP BLOCK DIAGRAM (SPI MODE) Internal data bus Read Write SSPBUF reg SSPSR reg RC4/SDI/SDA shift clock bit0 RC5/SDO SS Control Enable RA5/SS/AN4 Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TMR2 output 2 Prescaler TCY 4, 16, 64 TRISC<3> 1997 Microchip Technology Inc. Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 To enable the serial port, SSP enable bit SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear enable bit SSPEN, re-initialize SSPCON register, and then set enable bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRIS register) appropriately programmed. That is: * SDI must have TRISC<4> set * SDO must have TRISC<5> cleared * SCK (Master mode) must have TRISC<3> cleared * SCK (Slave mode) must have TRISC<3> set * SS must have TRISA<5> set (if implemented) Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. An example would be in master mode where you are only sending data (to a display driver), then both SDI and SS could be used as general purpose outputs by clearing their corresponding TRIS register bits. Figure 11-4 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2) is to broadcast data by the software protocol. In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SCK output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "line activity monitor" mode. In slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched interrupt flag bit SSPIF (PIR1<3>) is set. The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give waveforms for SPI communication as shown in Figure 11-5 and Figure 11-6 where the MSB is transmitted first. In master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * Fosc/4 (or TCY) Fosc/16 (or 4 * TCY) Fosc/64 (or 16 * TCY) Timer2 output/2 This allows a maximum bit clock frequency (at 20 MHz) of 5 MHz. When in slave mode the external clock must meet the minimum high and low times. In sleep mode, the slave can transmit and receive data and wake the device from sleep. * Master sends data -- Slave sends dummy data * Master sends data -- Slave sends data * Master sends dummy data -- Slave sends data FIGURE 11-4: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer (SSPBUF register) Serial Input Buffer (SSPBUF register) SDI Shift Register (SSPSR) MSb SDO LSb Shift Register (SSPSR) MSb LSb Serial Clock SCK PROCESSOR 1 1997 Microchip Technology Inc. SCK PROCESSOR 2 DS30390E-page 81 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 point at which it was taken high. External pull-up/ pull-down resistors may be desirable, depending on the application. The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set the for synchronous slave mode to be enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. If the SS pin is taken low without resetting SPI mode, the transmission will continue from the To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. FIGURE 11-5: SPI MODE TIMING, MASTER MODE OR SLAVE MODE W/O SS CONTROL SCK (CKP = 0) SCK (CKP = 1) bit7 SDO bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI bit7 bit0 SSPIF FIGURE 11-6: SPI MODE TIMING, SLAVE MODE WITH SS CONTROL SS SCK (CKP = 0) SCK (CKP = 1) bit6 bit7 SDO bit5 bit4 bit3 bit2 bit1 bit0 SDI bit7 bit0 SSPIF TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 5 Bit 4 T0IE INTE 0Bh,8Bh INTCON GIE PEIE 0Ch PIR1 PSPIF(1,2) ADIF RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1,2) ADIE RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON SSPOV SSPEN 85h TRISA -- -- 94h SSPSTAT -- -- CKP Bit 3 RBIE Bit 2 Bit 1 Bit 0 T0IF INTF RBIF Value on all other resets Name WCOL Bit 6 Value on: POR, BOR Address SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 PORTA Data Direction Register D/A P S R/W 0000 000x 0000 000u --11 1111 --11 1111 UA BF --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'. DS30390E-page 82 1997 Microchip Technology Inc. Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11.3 SPI Mode for PIC16C76/77 This section contains register definitions and operational characteristics of the SPI module on the PIC16C76 and PIC16C77 only. FIGURE 11-7: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)(PIC16C76/77) R/W-0 R/W-0 SMP CKE R-0 R-0 R-0 R-0 R-0 R-0 D/A P S R/W UA BF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset bit 7: SMP: SPI data input sample phase SPI Master Mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode bit 6: CKE: SPI Clock Edge Select (Figure 11-11, Figure 11-12, and Figure 11-13) CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty 1997 Microchip Technology Inc. DS30390E-page 83 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C76/77) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master mode, clock = FOSC/4 0001 = SPI master mode, clock = FOSC/16 0010 = SPI master mode, clock = FOSC/64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master mode (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled DS30390E-page 84 1997 Microchip Technology Inc. Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11.3.1 SPI MODE FOR PIC16C76/77 The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) RC5/SDO * Serial Data In (SDI) RC4/SDI/SDA * Serial Clock (SCK) RC3/SCK/SCL Additionally a fourth pin may be used when in a slave mode of operation: EXAMPLE 11-2: LOADING THE SSPBUF (SSPSR) REGISTER (PIC16C76/77) BCF STATUS, RP1 BSF STATUS, RP0 LOOP BTFSS SSPSTAT, BF GOTO BCF MOVF ;Specify Bank 1 ; ;Has data been ;received ;(transmit ;complete)? ;No ;Specify Bank 0 ;W reg = contents ; of SSPBUF ;Save in user RAM LOOP STATUS, RP0 SSPBUF, W * Slave Select (SS) RA5/SS/AN4 When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: * * * * Master Mode (SCK is the clock output) Slave Mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select Mode (Slave mode only) The SSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8-bits of data have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit BF (SSPSTAT<0>) and interrupt flag bit SSPIF (PIR1<3>) are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit WCOL (SSPCON<7>) will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally the SSP Interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 11-2 shows the loading of the SSPBUF (SSPSR) for data transmission. The shaded instruction is only required if the received data is meaningful. 1997 Microchip Technology Inc. MOVWF RXDATA MOVF TXDATA, W ;W reg = contents ; of TXDATA ;New data to xmit MOVWF SSPBUF The block diagram of the SSP module, when in SPI mode (Figure 11-9), shows that the SSPSR is not directly readable or writable, and can only be accessed from addressing the SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various status conditions. FIGURE 11-9: SSP BLOCK DIAGRAM (SPI MODE)(PIC16C76/77) Internal data bus Read Write SSPBUF reg SSPSR reg RC4/SDI/SDA shift clock bit0 RC5/SDO SS Control Enable RA5/SS/AN4 Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TMR2 output 2 Prescaler TCY 4, 16, 64 TRISC<3> DS30390E-page 85 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: * SDI must have TRISC<4> set * SDO must have TRISC<5> cleared * SCK (Master mode) must have TRISC<3> cleared * SCK (Slave mode) must have TRISC<3> set * SS must have TRISA<5> set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. An example would be in master mode where you are only sending data (to a display driver), then both SDI and SS could be used as general purpose outputs by clearing their corresponding TRIS register bits. The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2) is to broadcast data by the firmware protocol. In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SCK output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "line activity monitor" mode. In slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched the interrupt flag bit SSPIF (PIR1<3>) is set. The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give waveforms for SPI communication as shown in Figure 11-11, Figure 11-12, and Figure 11-13 where the MSB is transmitted first. In master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: Figure 11-10 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application firmware. This leads to three scenarios for data transmission: * * * * * Master sends data -- Slave sends dummy data * Master sends data -- Slave sends data * Master sends dummy data -- Slave sends data In sleep mode, the slave can transmit and receive data and wake the device from sleep. FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum bit clock frequency (at 20 MHz) of 5 MHz. When in slave mode the external clock must meet the minimum high and low times. FIGURE 11-10: SPI MASTER/SLAVE CONNECTION (PIC16C76/77) SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer (SSPBUF) Serial Input Buffer (SSPBUF) SDI Shift Register (SSPSR) MSb SDO LSb Shift Register (SSPSR) MSb LSb Serial Clock SCK PROCESSOR 1 DS30390E-page 86 SCK PROCESSOR 2 1997 Microchip Technology Inc. Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set for the synchronous slave mode to be enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. If the SS pin is taken low without resetting SPI mode, the transmission will continue from the point at which it was taken high. External pull-up/ pull-down resistors may be desirable, depending on the application. . Note: When the SPI is in Slave Mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set to VDD. Note: If the SPI is used in Slave Mode with CKE = '1', then the SS pin control must be enabled. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. FIGURE 11-11: SPI MODE TIMING, MASTER MODE (PIC16C76/77) SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit7 SDO bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 11-12: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) (PIC16C76/77) SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit7 SDO bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF 1997 Microchip Technology Inc. DS30390E-page 87 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 FIGURE 11-13: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) (PIC16C76/77) SS (not optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit3 bit4 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 11-2: Address REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16C76/77) Name Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL 85h TRISA 94h SSPSTAT 0Bh,8Bh. INTCON 10Bh,18Bh 0Ch SSPOV SSPEN CKP SSPM3 SSPM2 -- -- SMP CKE SSPM1 SSPM0 PORTA Data Direction Register D/A P S R/W 0000 000x 0000 000u 0000 0000 0000 0000 --11 1111 --11 1111 UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. DS30390E-page 88 1997 Microchip Technology Inc. Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 I 2CTM Overview 11.4 This section provides an overview of the Inter-Integrated Circuit (I 2C) bus, with Section 11.5 discussing the operation of the SSP module in I2C mode. The I 2C bus is a two-wire serial interface developed by the Philips Corporation. The original specification, or standard mode, was for data transfers of up to 100 Kbps. The enhanced specification (fast mode) is also supported. This device will communicate with both standard and fast mode devices if attached to the same bus. The clock will determine the data rate. The I 2C interface employs a comprehensive protocol to ensure reliable transmission and reception of data. When transmitting data, one device is the "master" which initiates transfer on the bus and generates the clock signals to permit that transfer, while the other device(s) acts as the "slave." All portions of the slave protocol are implemented in the SSP module's hardware, except general call support, while portions of the master protocol need to be addressed in the PIC16CXX software. Table 11-3 defines some of the I 2C bus terminology. For additional information on the I 2C interface specification, refer to the Philips document "The I 2C bus and how to use it." #939839340011, which can be obtained from the Philips Corporation. In the I 2C interface protocol each device has an address. When a master wishes to initiate a data transfer, it first transmits the address of the device that it wishes to "talk" to. All devices "listen" to see if this is their address. Within this address, a bit specifies if the master wishes to read-from/write-to the slave device. The master and slave are always in opposite modes (transmitter/receiver) of operation during a data transfer. That is they can be thought of as operating in either of these two relations: In both cases the master generates the clock signal. The output stages of the clock (SCL) and data (SDA) lines must have an open-drain or open-collector in order to perform the wired-AND function of the bus. External pull-up resistors are used to ensure a high level when no device is pulling the line down. The number of devices that may be attached to the I2C bus is limited only by the maximum bus loading specification of 400 pF. 11.4.1 During times of no data transfer (idle time), both the clock line (SCL) and the data line (SDA) are pulled high through the external pull-up resistors. The START and STOP conditions determine the start and stop of data transmission. The START condition is defined as a high to low transition of the SDA when the SCL is high. The STOP condition is defined as a low to high transition of the SDA when the SCL is high. Figure 11-14 shows the START and STOP conditions. The master generates these conditions for starting and terminating data transfer. Due to the definition of the START and STOP conditions, when data is being transmitted, the SDA line can only change state when the SCL line is low. FIGURE 11-14: START AND STOP CONDITIONS SDA SCL S Start Condition * Master-transmitter and Slave-receiver * Slave-transmitter and Master-receiver TABLE 11-3: INITIATING AND TERMINATING DATA TRANSFER P Change of Data Allowed Change of Data Allowed Stop Condition I2C BUS TERMINOLOGY Term Description Transmitter The device that sends the data to the bus. Receiver The device that receives the data from the bus. Master The device which initiates the transfer, generates the clock and terminates the transfer. Slave The device addressed by a master. Multi-master More than one master device in a system. These masters can attempt to control the bus at the same time without corrupting the message. Arbitration Procedure that ensures that only one of the master devices will control the bus. This ensure that the transfer data does not get corrupted. Synchronization Procedure where the clock signals of two or more devices are synchronized. 1997 Microchip Technology Inc. DS30390E-page 89 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 ADDRESSING I 2C DEVICES 11.4.2 FIGURE 11-17: SLAVE-RECEIVER ACKNOWLEDGE There are two address formats. The simplest is the 7-bit address format with a R/W bit (Figure 11-15). The more complex is the 10-bit address with a R/W bit (Figure 11-16). For 10-bit address format, two bytes must be transmitted with the first five bits specifying this to be a 10-bit address. Data Output by Transmitter Data Output by Receiver R/W ACK slave address S R/W ACK Sent by Slave Start Condition Read/Write pulse Acknowledge S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK If the slave needs to delay the transmission of the next byte, holding the SCL line low will force the master into a wait state. Data transfer continues when the slave releases the SCL line. This allows the slave to move the received data or fetch the data it needs to transfer before allowing the clock to start. This wait state technique can also be implemented at the bit level, Figure 11-18. The slave will inherently stretch the clock, when it is a transmitter, but will not when it is a receiver. The slave will have to clear the SSPCON<4> bit to enable clock stretching when it is a receiver. sent by slave = 0 for write 11.4.3 Clock Pulse for Acknowledgment If the master is receiving the data (master-receiver), it generates an acknowledge signal for each received byte of data, except for the last byte. To signal the end of data to the slave-transmitter, the master does not generate an acknowledge (not acknowledge). The slave then releases the SDA line so the master can generate the STOP condition. The master can also generate the STOP condition during the acknowledge pulse for valid termination of data transfer. FIGURE 11-16: I2C 10-BIT ADDRESS FORMAT S R/W ACK 9 8 2 1 S Start Condition LSb S acknowledge SCL from Master FIGURE 11-15: 7-BIT ADDRESS FORMAT MSb not acknowledge - Start Condition - Read/Write Pulse - Acknowledge TRANSFER ACKNOWLEDGE All data must be transmitted per byte, with no limit to the number of bytes transmitted per data transfer. After each byte, the slave-receiver generates an acknowledge bit (ACK) (Figure 11-17). When a slave-receiver doesn't acknowledge the slave address or received data, the master must abort the transfer. The slave must leave SDA high so that the master can generate the STOP condition (Figure 11-14). FIGURE 11-18: DATA TRANSFER WAIT STATE SDA MSB acknowledgment signal from receiver byte complete interrupt with receiver acknowledgment signal from receiver clock line held low while interrupts are serviced SCL S Start Condition DS30390E-page 90 1 2 Address 7 8 9 R/W ACK 1 Wait State 2 Data 3*8 9 ACK P Stop Condition 1997 Microchip Technology Inc. Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 SCL is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). This allows a master to send "commands" to the slave and then receive the requested information or to address a different slave device. This sequence is shown in Figure 11-21. Figure 11-19 and Figure 11-20 show Master-transmitter and Master-receiver data transfer sequences. When a master does not wish to relinquish the bus (by generating a STOP condition), a repeated START condition (Sr) must be generated. This condition is identical to the start condition (SDA goes high-to-low while FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE For 10-bit address: S Slave Address R/W A1 Slave Address A2 Second byte First 7 bits For 7-bit address: S Slave Address R/W A Data A Data A/A P '0' (write) data transferred (n bytes - acknowledge) A master transmitter addresses a slave receiver with a 7-bit address. The transfer direction is not changed. From master to slave From slave to master (write) Data A A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition Data A/A P A master transmitter addresses a slave receiver with a 10-bit address. FIGURE 11-20: MASTER-RECEIVER SEQUENCE For 10-bit address: For 7-bit address: S Slave Address R/W A1 Slave Address A2 Second byte First 7 bits S Slave Address R/W A Data A Data A P '1' (read) data transferred (n bytes - acknowledge) A master reads a slave immediately after the first byte. From master to slave From slave to master (write) A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition Sr Slave Address R/W A3 Data A First 7 bits Data A P (read) A master transmitter addresses a slave receiver with a 10-bit address. FIGURE 11-21: COMBINED FORMAT (read or write) (n bytes + acknowledge) S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P (read) Sr = repeated Start Condition (write) Direction of transfer may change at this point Transfer direction of data and acknowledgment bits depends on R/W bits. Combined format: Sr Slave Address R/W A Slave Address A Data A First 7 bits Second byte Data A/A Sr Slave Address R/W A Data A First 7 bits Data A P (read) (write) Combined format - A master addresses a slave with a 10-bit address, then transmits data to this slave and reads data from this slave. From master to slave From slave to master 1997 Microchip Technology Inc. A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition DS30390E-page 91 Applicable Devices PIC16C7X 11.4.4 72 73 73A 74 74A 76 77 MULTI-MASTER 11.2.4.2 Clock Synchronization The I2C protocol allows a system to have more than one master. This is called multi-master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur. 11.4.4.1 ARBITRATION Arbitration takes place on the SDA line, while the SCL line is high. The master which transmits a high when the other master transmits a low loses arbitration (Figure 11-22), and turns off its data output stage. A master which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration. When the master devices are addressing the same device, arbitration continues into the data. FIGURE 11-22: MULTI-MASTER ARBITRATION (TWO MASTERS) Clock synchronization occurs after the devices have started arbitration. This is performed using a wired-AND connection to the SCL line. A high to low transition on the SCL line causes the concerned devices to start counting off their low period. Once a device clock has gone low, it will hold the SCL line low until its SCL high state is reached. The low to high transition of this clock may not change the state of the SCL line, if another device clock is still within its low period. The SCL line is held low by the device with the longest low period. Devices with shorter low periods enter a high wait-state, until the SCL line comes high. When the SCL line comes high, all devices start counting off their high periods. The first device to complete its high period will pull the SCL line low. The SCL line high time is determined by the device with the shortest high period, Figure 11-23. FIGURE 11-23: CLOCK SYNCHRONIZATION transmitter 1 loses arbitration DATA 1 SDA wait state DATA 1 DATA 2 start counting HIGH period CLK 1 SDA CLK 2 counter reset SCL SCL Masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode. This is because the winning master-transmitter may be addressing it. Arbitration is not allowed between: * A repeated START condition * A STOP condition and a data bit * A repeated START condition and a STOP condition Care needs to be taken to ensure that these conditions do not occur. DS30390E-page 92 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 11.5 SSP I 2C Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>). FIGURE 11-24: SSP BLOCK DIAGRAM (I2C MODE) Internal data bus Read Write SSPBUF reg RC3/SCK/SCL shift clock SSPSR reg RC4/ SDI/ SDA MSb LSb Match detect Addr Match SSPADD reg Start and Stop bit detect Set, Reset S, P bits (SSPSTAT reg) The SSP module has five registers for I2C operation. These are the: PIC16C7X The SSPCON register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address), with start and stop bit interrupts enabled * I 2C Slave mode (10-bit address), with start and stop bit interrupts enabled * I 2C Firmware controlled Master Mode, slave is idle Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. The SSPSTAT register gives the status of the data transfer. This information includes detection of a START or STOP bit, specifies if the received byte was data or address if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. The SSPSTAT register is read only. The SSPBUF is the register to which transfer data is written to or read from. The SSPSR register shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a doubled buffered receiver. This allows reception of the next byte to begin before reading the last byte of received data. When the complete byte is received, it is transferred to the SSPBUF register and flag bit SSPIF is set. If another complete byte is received before the SSPBUF register is read, a receiver overflow has occurred and bit SSPOV (SSPCON<6>) is set and the byte in the SSPSR is lost. The SSPADD register holds the slave address. In 10-bit mode, the user first needs to write the high byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of the address needs to be loaded (A7:A0). * * * * SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible * SSP Address Register (SSPADD) 1997 Microchip Technology Inc. DS30390E-page 93 Applicable Devices PIC16C7X 11.5.1 72 73 73A 74 74A 76 77 SLAVE MODE In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the SSP module not to give this ACK pulse. These are if either (or both): a) b) The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 11-4 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification as well as the requirement of the SSP module is shown in timing parameter #100 and parameter #101. 11.5.1.1 address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) In 10-bit address mode, two address bytes need to be received by the slave (Figure 11-16). The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. 2. 3. 4. 5. ADDRESSING Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The TABLE 11-4: The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth SCL pulse. 6. 7. 8. 9. Receive first (high) byte of Address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address, if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated START condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF (SSP Interrupt occurs if enabled) BF SSPOV SSPSR SSPBUF Generate ACK Pulse 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes DS30390E-page 94 1997 Microchip Technology Inc. Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11.5.1.2 An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. FIGURE 11-25: I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address Receiving Data R/W=0 Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL S 1 2 3 4 5 6 SSPIF (PIR1<3>) BF (SSPSTAT<0>) 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 Cleared in software 9 P Bus Master terminates transfer SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. 1997 Microchip Technology Inc. DS30390E-page 95 Applicable Devices PIC16C7X 11.5.1.3 72 73 73A 74 74A 76 77 TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 11-26). An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP. FIGURE 11-26: I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address SDA SCL A7 S A6 1 2 Data in sampled SSPIF (PIR1<3>) R/W = 1 A5 A4 A3 A2 A1 3 4 5 6 7 8 9 ACK Transmitting Data ACK D7 1 SCL held low while CPU responds to SSPIF D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P cleared in software BF (SSPSTAT<0>) SSPBUF is written in software From SSP interrupt service routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) DS30390E-page 96 1997 Microchip Technology Inc. Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11.5.2 11.5.3 MASTER MODE In multi-master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. Master mode of operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle and both the S and P bits are clear. In master mode the SCL and SDA lines are manipulated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit. In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are: The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): * Address Transfer * Data Transfer * START condition * STOP condition * Data transfer byte transmitted/received When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. Master mode of operation can be done with either the slave mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master and slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. TABLE 11-5: MULTI-MASTER MODE REGISTERS ASSOCIATED WITH I2C OPERATION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets 0Bh, 8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN 0000 0000 0000 0000 94h SSPSTAT SMP(2) CKE(2) 0000 0000 0000 0000 87h TRISC 1111 1111 1111 1111 D/A PORTC Data Direction register CKP P SSPM3 SSPM2 SSPM1 SSPM0 S R/W UA BF Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: PSPIF and PSPIE are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The SMP and CKE bits are implemented on the PIC16C76/77 only. All other PIC16C7X devices have these two bits unimplemented, read as '0'. 1997 Microchip Technology Inc. DS30390E-page 97 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 FIGURE 11-27: OPERATION OF THE I 2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE IDLE_MODE (7-bit): if (Addr_match) { Set interrupt; if (R/W = 1) { Send ACK = 0; set XMIT_MODE; } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((SSPBUF=Full) OR (SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { transfer SSPSR SSPBUF; send ACK = 0; } Receive 8-bits in SSPSR; Set interrupt; XMIT_MODE: While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if ( ACK Received = 1) { End of transmission; Go back to IDLE_MODE; } else if ( ACK Received = 0) Go back to XMIT_MODE; IDLE_MODE (10-Bit): If (High_byte_addr_match AND (R/W = 0)) { PRIOR_ADDR_MATCH = FALSE; Set interrupt; if ((SSPBUF = Full) OR ((SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { Set UA = 1; Send ACK = 0; While (SSPADD not updated) Hold SCL low; Clear UA = 0; Receive Low_addr_byte; Set interrupt; Set UA = 1; If (Low_byte_addr_match) { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear UA = 0; Set RCV_MODE; } } } else if (High_byte_addr_match AND (R/W = 1) { if (PRIOR_ADDR_MATCH) { send ACK = 0; set XMIT_MODE; } else PRIOR_ADDR_MATCH = FALSE; } DS30390E-page 98 1997 Microchip Technology Inc. PIC16C7X 12.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc. The USART can be configured in the following modes: Applicable Devices 72 73 73A 74 74A 76 77 * Asynchronous (full duplex) * Synchronous - Master (half duplex) * Synchronous - Slave (half duplex) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to be set in order to configure pins RC6/TX/CK and RC7/ RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. FIGURE 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 CSRC bit7 bit 7: R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset CSRC: Clock Source Select bit Asynchronous mode Don't care Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) bit 6: TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5: TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4: SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3: Unimplemented: Read as '0' bit 2: BRGH: High Baud Rate Select bit Asynchronous mode 1 = High speed Note: For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77. 0 = Low speed Synchronous mode Unused in this mode bit 1: TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit. 1997 Microchip Technology Inc. DS30390E-page 99 PIC16C7X FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 SPEN bit7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN U-0 -- R-0 FERR R-0 OERR R-x RX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset bit 7: SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6: RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5: SREN: Single Receive Enable bit Asynchronous mode Don't care Synchronous mode - master 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave Unused in this mode bit 4: CREN: Continuous Receive Enable bit Asynchronous mode 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3: Unimplemented: Read as '0' bit 2: FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1: OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30390E-page 100 1997 Microchip Technology Inc. PIC16C7X 12.1 USART Baud Rate Generator (BRG) EXAMPLE 12-1: CALCULATING BAUD RATE ERROR Applicable Devices 72 73 73A 74 74A 76 77 Desired Baud rate = Fosc / (64 (X + 1)) The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In asynchronous mode bit BRGH (TXSTA<2>) also controls the baud rate. In synchronous mode bit BRGH is ignored. Table 12-1 shows the formula for computation of the baud rate for different USART modes which only apply in master mode (internal clock). 9600 = 16000000 /(64 (X + 1)) X 25.042 = 25 = Calculated Baud Rate=16000000 / (64 (25 + 1)) = Error Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be calculated using the formula in Table 12-1. From this, the error in baud rate can be determined. = 9615 (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600) / 9600 = 0.16% It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Example 12-1 shows the calculation of the baud rate error for the following conditions: FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0 Note: For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77. Writing a new value to the SPBRG register, causes the BRG timer to be reset (or cleared), this ensures the BRG does not wait for a timer overflow before outputting the new baud rate. TABLE 12-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) X = value in SPBRG (0 to 255) Baud Rate= FOSC/(16(X+1)) NA 0 1 TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 0 Value on: POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 98h TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 0000 -010 0000 -010 18h RCSTA SPEN RX9 SREN CREN -- FERR OERR RX9D 0000 -00x 0000 -00x 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG. 1997 Microchip Technology Inc. DS30390E-page 101 PIC16C7X TABLE 12-3: BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR SYNCHRONOUS MODE FOSC = 20 MHz KBAUD NA NA NA NA 19.53 76.92 96.15 294.1 500 5000 19.53 16 MHz SPBRG value % KBAUD ERROR (decimal) +1.73 +0.16 +0.16 -1.96 0 - 255 64 51 16 9 0 255 FOSC = 5.0688 MHz BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW +0.16 +0.16 -0.79 +2.56 0 - 207 51 41 12 7 0 255 4 MHz NA NA NA 9.766 19.23 75.76 96.15 312.5 500 2500 9.766 7.15909 MHz SPBRG SPBRG value value % % KBAUD ERROR (decimal) ERROR (decimal) +1.73 +0.16 -1.36 +0.16 +4.17 0 - 255 129 32 25 7 4 0 255 3.579545 MHz NA NA NA 9.622 19.24 77.82 94.20 298.3 NA 1789.8 6.991 +0.23 +0.23 +1.32 -1.88 -0.57 - 1 MHz 185 92 22 18 5 0 255 32.768 kHz SPBRG SPBRG SPBRG SPBRG SPBRG KBAUD % value KBAUD % value KBAUD % value KBAUD % value KBAUD % value ERROR (decimal) ERROR (decimal) ERROR (decimal) ERROR (decimal) ERROR (decimal) NA NA NA 9.6 19.2 79.2 97.48 316.8 NA 1267 4.950 TABLE 12-4: BAUD RATE (K) NA NA NA NA 19.23 76.92 95.24 307.69 500 4000 15.625 10 MHz SPBRG value % KBAUD ERROR (decimal) 0 0 +3.13 +1.54 +5.60 - 131 65 15 12 3 0 255 NA NA NA 9.615 19.231 76.923 1000 NA NA 100 3.906 NA 1.221 2.404 9.469 19.53 78.13 104.2 312.5 NA 312.5 1.221 103 51 12 9 0 255 NA NA NA 9.622 19.04 74.57 99.43 298.3 NA 894.9 3.496 +0.23 -0.83 -2.90 +3.57 -0.57 - 92 46 11 8 2 0 255 NA 1.202 2.404 9.615 19.24 83.34 NA NA NA 250 0.9766 +0.16 +0.16 +0.16 +0.16 +8.51 - 207 103 25 12 2 0 255 0.303 1.170 NA NA NA NA NA NA NA 8.192 0.032 +1.14 -2.48 - 26 6 0 255 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz KBAUD +0.16 +0.16 +0.16 +4.17 - 16 MHz SPBRG % value ERROR (decimal) KBAUD +1.73 +0.16 -1.36 +1.73 +1.73 +8.51 +4.17 - 255 129 32 15 3 2 0 0 255 FOSC = 5.0688 MHz NA 1.202 2.404 9.615 19.23 83.33 NA NA NA 250 0.977 10 MHz SPBRG % value ERROR (decimal) KBAUD +0.16 +0.16 +0.16 +0.16 +8.51 - 207 103 25 12 2 0 255 4 MHz NA 1.202 2.404 9.766 19.53 78.13 NA NA NA 156.3 0.6104 7.15909 MHz SPBRG SPBRG % value % value ERROR (decimal) KBAUD ERROR (decimal) +0.16 +0.16 +1.73 +1.73 +1.73 - 3.579545 MHz 129 64 15 7 1 0 255 NA 1.203 2.380 9.322 18.64 NA NA NA NA 111.9 0.437 +0.23 -0.83 -2.90 -2.90 - 1 MHz 92 46 11 5 0 255 32.768 kHz BAUD RATE (K) SPBRG SPBRG SPBRG SPBRG SPBRG % value % value % value % value % value KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW 0.31 1.2 2.4 9.9 19.8 79.2 NA NA NA 79.2 0.3094 +3.13 0 0 +3.13 +3.13 +3.13 - DS30390E-page 102 255 65 32 7 3 0 0 255 0.3005 1.202 2.404 NA NA NA NA NA NA 62.500 3.906 -0.17 +1.67 +1.67 - 207 51 25 0 255 0.301 1.190 2.432 9.322 18.64 NA NA NA NA 55.93 0.2185 +0.23 -0.83 +1.32 -2.90 -2.90 - 185 46 22 5 2 0 255 0.300 1.202 2.232 NA NA NA NA NA NA 15.63 0.0610 +0.16 +0.16 -6.99 - 51 12 6 0 255 0.256 NA NA NA NA NA NA NA NA 0.512 0.0020 -14.67 - 1 0 255 1997 Microchip Technology Inc. PIC16C7X TABLE 12-5: BAUD RATE (K) 9.6 19.2 38.4 57.6 115.2 250 625 1250 BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz KBAUD 9.615 19.230 37.878 56.818 113.636 250 625 1250 16 MHz SPBRG % value ERROR (decimal) KBAUD +0.16 +0.16 -1.36 -1.36 -1.36 0 0 0 129 64 32 21 10 4 1 0 9.615 19.230 38.461 58.823 111.111 250 NA NA 10 MHz SPBRG % value ERROR (decimal) KBAUD +0.16 +0.16 +0.16 +2.12 -3.55 0 - 103 51 25 16 8 3 - 9.615 18.939 39.062 56.818 125 NA 625 NA 7.16 MHz SPBRG SPBRG % value % value ERROR (decimal) KBAUD ERROR (decimal) +0.16 -1.36 +1.7 -1.36 +8.51 0 - 64 32 15 10 4 0 - 9.520 19.454 37.286 55.930 111.860 NA NA NA -0.83 +1.32 -2.90 -2.90 -2.90 - 46 22 11 7 3 - FOSC = 5.068 MHz 4 MHz 3.579 MHz 1 MHz 32.768 kHz SPBRG SPBRG SPBRG SPBRG SPBRG % value % value % value % value % value KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 9.6 19.2 9.6 18.645 0 -2.94 32 16 NA 1.202 38.4 57.6 115.2 250 625 1250 39.6 52.8 105.6 NA NA NA +3.12 -8.33 -8.33 - 7 5 2 - 2.403 9.615 19.231 NA NA NA Note: +0.17 +0.13 +0.16 +0.16 - 207 9.727 18.643 +1.32 -2.90 22 11 8.928 20.833 -6.99 +8.51 6 2 NA NA - - 103 25 12 - 37.286 -2.90 55.930 -2.90 111.860 -2.90 223.721 -10.51 NA NA - 5 3 1 0 - 31.25 62.5 NA NA NA NA -18.61 +8.51 - 1 0 - NA NA NA NA NA NA - - For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77. 1997 Microchip Technology Inc. DS30390E-page 103 PIC16C7X 12.1.1 set (i.e., at the high baud rates), the sampling is done on the 3 clock edges preceding the second rising edge after the first falling edge of a x4 clock (Figure 12-4 and Figure 12-5). SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. If bit BRGH (TXSTA<2>) is clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth falling edges of a x16 clock (Figure 12-3). If bit BRGH is FIGURE 12-3: RX PIN SAMPLING SCHEME. BRGH = 0 (PIC16C73/73A/74/74A) Start bit RX (RC7/RX/DT pin) Bit0 Baud CLK for all but start bit baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A) RX pin bit0 Start Bit bit1 baud clk First falling edge after RX pin goes low Second rising edge x4 clk 1 2 3 4 1 2 3 4 1 2 Q2, Q4 clk Samples Samples Samples FIGURE 12-5: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A) RX pin Start Bit bit0 Baud clk for all but start bit baud clk First falling edge after RX pin goes low Second rising edge x4 clk 1 2 3 4 Q2, Q4 clk Samples DS30390E-page 104 1997 Microchip Technology Inc. PIC16C7X FIGURE 12-6: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 (PIC16C76/77) Start bit RX (RC7/RX/DT pin) Bit0 Baud CLK for all but start bit baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples 1997 Microchip Technology Inc. DS30390E-page 105 PIC16C7X 12.2 USART Asynchronous Mode flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Applicable Devices 72 73 73A 74 74A 76 77 In this mode, the USART uses standard nonreturn-tozero (NRZ) format (one start bit, eight or nine data bits and one stop bit). The most common data format is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART's transmitter and receiver are functionally independent but use the same data format and baud rate. The baud rate generator produces a clock either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Note 1: The TSR register is not mapped in data memory so it is not available to the user. Note 2: Flag bit TXIF is set when enable bit TXEN is set. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the baud rate generator (BRG) has produced a shift clock (Figure 12-7). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. Normally when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. A back-toback transfer is thus possible (Figure 12-9). Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result the RC6/TX/CK pin will revert to hiimpedance. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver 12.2.1 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 12-7. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and In order to select 9-bit transmission, transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit maybe loaded in the TSR register. FIGURE 12-7: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb LSb * * * (8) Pin Buffer and Control 0 TSR register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG Baud Rate Generator TX9 TX9D DS30390E-page 106 1997 Microchip Technology Inc. PIC16C7X Steps to follow when setting up an Asynchronous Transmission: 4. 1. 5. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 12.1) Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. 2. 3. If 9-bit transmission is desired, then set transmit bit TX9. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). 6. 7. FIGURE 12-8: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG Word 1 BRG output (shift clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit WORD 1 TXIF bit (Transmit buffer reg. empty flag) WORD 1 Transmit Shift Reg TRMT bit (Transmit shift reg. empty flag) FIGURE 12-9: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 BRG output (shift clock) RC6/TX/CK (pin) TXIF bit (interrupt reg. flag) TRMT bit (Transmit shift reg. empty flag) Word 2 Start Bit Bit 0 Bit 1 WORD 1 Bit 7/8 Stop Bit Start Bit Bit 0 WORD 2 WORD 1 Transmit Shift Reg. WORD 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on: POR, BOR Value on all other Resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 18h RCSTA 19h TXREG USART Transmit Register 8Ch PIE1 SPEN PSPIE(1) RX9 ADIE SREN RCIE CREN TXIE -- FERR SSPIE CCP1IE OERR TMR2IE TMR1IE 0000 -010 0000 -010 98h TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc. DS30390E-page 107 PIC16C7X 12.2.2 double buffered register, i.e. it is a two deep FIFO. It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full then overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited, so it is essential to clear error bit OERR if it is set. Framing error bit FERR (RCSTA<2>) is set if a stop bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same way as the receive data. Reading the RCREG, will load bits RX9D and FERR with new values, therefore it is essential for the user to read the RCSTA register before reading RCREG register in order not to lose the old FERR and RX9D information. USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 12-10. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the receive (serial) shift register (RSR). After sampling the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty). If the transfer is complete, flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG is a FIGURE 12-10: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK FERR OERR CREN SPBRG / 64 or / 16 Baud Rate Generator RSR register MSb Stop (8) * * * 7 1 LSb 0 Start RC7/RX/DT Pin Buffer and Control Data Recovery RX9 RX9D SPEN RCREG register FIFO 8 RCIF Interrupt Data Bus RCIE FIGURE 12-11: ASYNCHRONOUS RECEPTION RX (pin) Rcv shift reg Rcv buffer reg Read Rcv buffer reg RCREG Start bit bit0 bit1 bit7/8 Stop bit Start bit WORD 1 RCREG bit0 bit7/8 Stop bit Start bit bit7/8 Stop bit WORD 2 RCREG RCIF (interrupt flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS30390E-page 108 1997 Microchip Technology Inc. PIC16C7X 6. Steps to follow when setting up an Asynchronous Reception: 1. 2. 3. 4. 5. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 12.1). Enable the asynchronous serial port by clearing bit SYNC, and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN. TABLE 12-7: Address Name 7. 8. 9. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing enable bit CREN. REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 PSPIF(1) ADIF RCIF TXIF SPEN RX9 SREN CREN 0Ch PIR1 18h RCSTA 1Ah RCREG USART Receive Register 8Ch PIE1 98h TXSTA 99h SPBRG Bit 4 PSPIE(1) ADIE RCIE TXIE CSRC TX9 TXEN SYNC Baud Rate Generator Register Bit 3 Bit 2 SSPIF CCP1IF -- FERR Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets TMR2IF TMR1IF 0000 0000 0000 0000 OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE -- BRGH TRMT Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc. DS30390E-page 109 PIC16C7X 12.3 USART Synchronous Master Mode Applicable Devices 72 73 73A 74 74A 76 77 In Synchronous Master mode, the data is transmitted in a half-duplex manner i.e. transmission and reception do not occur at the same time. When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>). 12.3.1 USART SYNCHRONOUS MASTER TRANSMISSION The USART transmitter block diagram is shown in Figure 12-7. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one Tcycle), the TXREG is empty and interrupt bit, TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. TRMT is a read only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. Clearing enable bit TXEN, during a transmission, will cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to hi-impedance. If either bit CREN or bit SREN is set, during a transmission, the transmission is aborted and the DT pin reverts to a hi-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock). The transmitter logic however is not reset although it is disconnected from the pins. In order to reset the transmitter, the user has to clear bit TXEN. If bit SREN is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit SREN will be cleared and the serial port will revert back to transmitting since bit TXEN is still set. The DT line will immediately switch from hi-impedance receive mode to transmit and start driving. To avoid this, bit TXEN should be cleared. In order to select 9-bit transmission, the TX9 (TXSTA<6>) bit should be set and the ninth bit should be written to bit TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register (if the TSR is empty). If the TSR was empty and the TXREG was written before writing the "new" TX9D, the "present" value of bit TX9D is loaded. Steps to follow when setting up a Synchronous Master Transmission: 1. 2. 3. 4. 5. 6. 7. Initialize the SPBRG register for the appropriate baud rate (Section 12.1). Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure 12-12). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 12-13). This is advantageous when slow baud rates are selected, since the BRG is kept in reset when bits TXEN, CREN, and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible. DS30390E-page 110 1997 Microchip Technology Inc. PIC16C7X TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 18h RCSTA SPEN RX9 SREN CREN -- FERR OERR 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 99h SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. FIGURE 12-12: SYNCHRONOUS TRANSMISSION Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 RC7/RX/DT pin Bit 0 Bit 1 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 Bit 2 Bit 7 Bit 0 WORD 1 Bit 1 WORD 2 Bit 7 RC6/TX/CK pin Write to TXREG reg Write word1 Write word2 TXIF bit (Interrupt flag) TRMT TRMT bit TXEN bit '1' '1' Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words FIGURE 12-13: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit 1997 Microchip Technology Inc. DS30390E-page 111 PIC16C7X 12.3.2 Steps to follow when setting up a Synchronous Master Reception: USART SYNCHRONOUS MASTER RECEPTION 1. Initialize the SPBRG register for the appropriate baud rate. (Section 12.1) 2. Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set then CREN takes precedence. After clocking the last bit, the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). When the transfer is complete, interrupt flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit which is reset by the hardware. In this case it is reset when the RCREG register has been read and is empty. The RCREG is a double buffered register, i.e. it is a two deep FIFO. It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. On the clocking of the last bit of the third byte, if the RCREG register is still full then overrun error bit OERR (RCSTA<1>) is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The 9th receive bit is buffered the same way as the receive data. Reading the RCREG register, will load bit RX9D with a new value, therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 18h RCSTA SPEN RX9 SREN CREN -- FERR OERR 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 99h SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. DS30390E-page 112 1997 Microchip Technology Inc. PIC16C7X FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'. 1997 Microchip Technology Inc. DS30390E-page 113 PIC16C7X 12.4 USART Synchronous Slave Mode Applicable Devices 72 73 73A 74 74A 76 77 Synchronous slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 12.4.1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the synchronous master and slave modes are identical except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) e) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). Steps to follow when setting up a Synchronous Slave Transmission: 1. 2. 3. 4. 5. 6. 7. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. DS30390E-page 114 12.4.2 USART SYNCHRONOUS SLAVE RECEPTION The operation of the synchronous master and slave modes is identical except in the case of the SLEEP mode. Also, bit SREN is a don't care in slave mode. If receive is enabled, by setting bit CREN, prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h). Steps to follow when setting up a Synchronous Slave Reception: 1. 2. 3. 4. 5. 6. 7. 8. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. 1997 Microchip Technology Inc. PIC16C7X TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 18h RCSTA SPEN RX9 SREN CREN -- FERR OERR 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 99h SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN -- FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 1Ah RCREG USART Receive Register 8Ch PIE1 PSPIE(1) 98h TXSTA CSRC ADIE TX9 RCIE TXEN TXIE SYNC SSPIE -- CCP1IE BRGH TMR2IE TRMT 0000 0000 0000 0000 99h SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc. DS30390E-page 115 PIC16C7X NOTES: DS30390E-page 116 1997 Microchip Technology Inc. PIC16C7X 13.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. Applicable Devices 72 73 73A 74 74A 76 77 The analog-to-digital (A/D) converter module has five inputs for the PIC16C72/73/73A/76, and eight for the PIC16C74/74A/77. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD) or the voltage level on the RA3/AN3/VREF pin. The A/D module has three registers. These registers are: * A/D Result Register (ADRES) * A/D Control Register 0 (ADCON0) * A/D Control Register 1 (ADCON1) The ADCON0 register, shown in Figure 13-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 13-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as digital I/O. FIGURE 13-1: ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 R/W-0 ADCS1 ADCS0 bit7 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an internal RC oscillator) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) 101 = channel 5, (RE0/AN5)(1) 110 = channel 6, (RE1/AN6)(1) 111 = channel 7, (RE2/AN7)(1) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: A/D channels 5, 6, and 7 are implemented on the PIC16C74/74A/77 only. 1997 Microchip Technology Inc. DS30390E-page 117 PIC16C7X FIGURE 13-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 -- bit7 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D RE0(1) RE1(1) RE2(1) A A D D D D D A A D D D D D A A D D D D D VREF VDD RA3 VDD RA3 VDD RA3 -- A = Analog input D = Digital I/O Note 1: RE0, RE1, and RE2 are implemented on the PIC16C74/74A/77 only. DS30390E-page 118 1997 Microchip Technology Inc. PIC16C7X 3. 4. The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagrams of the A/D module are shown in Figure 13-3. 5. OR After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 13.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. 2. Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared 6. 7. * Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts. Configure the A/D module: * Configure analog pins / voltage reference / and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit FIGURE 13-3: A/D BLOCK DIAGRAM CHS2:CHS0 111 110 101 RE2/AN7(1) RE1/AN6(1) RE0/AN5(1) 100 RA5/AN4 VIN 011 (Input voltage) RA3/AN3/VREF 010 RA2/AN2 A/D Converter 001 RA1/AN1 VDD 000 RA0/AN0 000 or 010 or 100 VREF (Reference voltage) 001 or 011 or 101 PCFG2:PCFG0 Note 1: Not available on PIC16C72/73/73A/76. 1997 Microchip Technology Inc. DS30390E-page 119 PIC16C7X 13.1 A/D Acquisition Requirements VDD = 5V Rss = 7 k Applicable Devices 72 73 73A 74 74A 76 77 Temp (application system max.) = 50C VHOLD = 0 @ t = 0 For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 13-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), Figure 13-4. The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 13-1 may be used. This equation calculates the acquisition time to within 1/2 LSb error is used (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy. EQUATION 13-1: A/D MINIMUM CHARGING TIME Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. Note 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. Note 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. Note 4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again. During this time the holding capacitor is not connected to the selected A/D input channel. EXAMPLE 13-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + VHOLD = (VREF - (VREF/512)) * (1 - e(-TCAP/CHOLD(RIC + RSS + RS))) Given: VHOLD = (VREF/512), for 1/2 LSb resolution Temperature Coefficient TACQ = 5 s + TCAP + [(Temp - 25C)(0.05 s/C)] The above equation reduces to: TCAP = -CHOLD (RIC + RSS + RS) ln(1/511) TCAP = -(51.2 pF)(1 k + RSS + RS) ln(1/511) -51.2 pF (1 k + 7 k + 10 k) ln(0.0020) Example 13-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following system assumptions. -51.2 pF (18 k) ln(0.0020) -0.921 s (-6.2364) 5.747 s TACQ = 5 s + 5.747 s + [(50C - 25C)(0.05 s/C)] CHOLD = 51.2 pF Rs = 10 k 10.747 s + 1.25 s 1/2 LSb error 11.997 s FIGURE 13-4: ANALOG INPUT MODEL VDD Rs ANx CPIN 5 pF VA Sampling Switch VT = 0.6V VT = 0.6V RIC 1k SS RSS CHOLD = DAC capacitance = 51.2 pF I leakage 500 nA VSS Legend CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC SS CHOLD DS30390E-page 120 = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) 6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch ( k ) 1997 Microchip Technology Inc. PIC16C7X 13.2 Selecting the A/D Conversion Clock 13.3 Configuring Analog Port Pins Applicable Devices 72 73 73A 74 74A 76 77 Applicable Devices 72 73 73A 74 74A 76 77 The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: * * * * 2TOSC 8TOSC 32TOSC Internal RC oscillator The ADCON1, TRISA, and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 13-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN7:AN0 pins), may cause the input buffer to consume current that is out of the devices specification. TABLE 13-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Operation ADCS1:ADCS0 2TOSC 00 8TOSC 01 32TOSC 10 RC(5) Legend: Note 1: 2: 3: 4: 5: Device Frequency 20 MHz 100 ns(2) ns(2) 400 1.6 s 5 MHz ns(2) 400 1.6 s 6.4 s 333.33 kHz 1.6 s 6 s 6.4 s 24 s(3) 25.6 s(3) 96 s(3) 2-6 2-6 2 - 6 s(1) 2 - 6 s Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. For extended voltage devices (LC), please refer to Electrical Specifications section. 11 1997 Microchip Technology Inc. (1,4) s(1,4) 1.25 MHz s(1,4) DS30390E-page 121 PIC16C7X 13.4 A/D Conversions Applicable Devices 72 73 73A 74 74A 76 77 Note: Example 13-2 shows how to perform an A/D conversion. The RA pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled, and the A/D conversion clock is FRC. The conversion is performed on the RA0 pin (channel 0). The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, an acquisition is automatically started on the selected channel. EXAMPLE 13-2: A/D CONVERSION BSF BCF CLRF BSF BCF MOVLW MOVWF BCF BSF BSF ; ; ; ; STATUS, STATUS, ADCON1 PIE1, STATUS, 0xC1 ADCON0 PIR1, INTCON, INTCON, RP0 RP1 ADIE RP0 ADIF PEIE GIE ; ; ; ; ; ; ; ; ; ; Select Bank 1 PIC16C76/77 only Configure A/D inputs Enable A/D interrupts Select Bank 0 RC Clock, A/D is on, Channel 0 is selected Clear A/D interrupt flag bit Enable peripheral interrupts Enable all interrupts Ensure that the required sampling time for the selected input channel has elapsed. Then the conversion may be started. BSF : : ADCON0, GO DS30390E-page 122 ; Start A/D Conversion ; The ADIF bit will be set and the GO/DONE bit ; is cleared upon completion of the A/D Conversion. 1997 Microchip Technology Inc. PIC16C7X 13.4.1 FASTER CONVERSION - LOWER RESOLUTION TRADE-OFF Not all applications require a result with 8-bits of resolution, but may instead require a faster conversion time. The A/D module allows users to make the trade-off of conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same. To speed up the conversion, the clock source of the A/D module may be switched so that the TAD time violates the minimum specified time (see the applicable electrical specification). Once the TAD time violates the minimum specified time, all the following A/D result bits are not valid (see A/D Conversion Timing in the Electrical Specifications section.) The clock sources may only be switched between the three oscillator versions (cannot be switched from/to RC). The equation to determine the time before the oscillator can be switched is as follows: Since the TAD is based from the device oscillator, the user must use some method (a timer, software loop, etc.) to determine when the A/D oscillator may be changed. Example 13-3 shows a comparison of time required for a conversion with 4-bits of resolution, versus the 8-bit resolution conversion. The example is for devices operating at 20 MHz and 16 MHz (The A/D clock is programmed for 32TOSC), and assumes that immediately after 6TAD, the A/D clock is programmed for 2TOSC. The 2TOSC violates the minimum TAD time since the last 4-bits will not be converted to correct values. Conversion time = 2TAD + N * TAD + (8 - N)(2TOSC) Where: N = number of bits of resolution required. EXAMPLE 13-3: 4-BIT vs. 8-BIT CONVERSION TIMES Freq. (MHz)(1) TAD TOSC 2TAD + N * TAD + (8 - N)(2TOSC) 20 16 20 16 20 16 Resolution 4-bit 8-bit 1.6 s 2.0 s 50 ns 62.5 ns 10 s 12.5 s 1.6 s 2.0 s 50 ns 62.5 ns 16 s 20 s Note 1: PIC16C7X devices have a minimum TAD time of 1.6 s. 1997 Microchip Technology Inc. DS30390E-page 123 PIC16C7X 13.5 A/D Operation During Sleep Applicable Devices 72 73 73A 74 74A 76 77 The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: 13.6 For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit. A/D Accuracy/Error Applicable Devices 72 73 73A 74 74A 76 77 The absolute accuracy specified for the A/D converter includes the sum of all contributions for quantization error, integral error, differential error, full scale error, offset error, and monotonicity. It is defined as the maximum deviation from an actual transition versus an ideal transition for any code. The absolute error of the A/D converter is specified at < 1 LSb for VDD = VREF (over the device's specified operating range). However, the accuracy of the A/D converter will degrade as VDD diverges from VREF. Gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. This error appears as a change in slope of the transfer function. The difference in gain error to full scale error is that full scale does not take offset error into account. Gain error can be calibrated out in software. Linearity error refers to the uniformity of the code changes. Linearity errors cannot be calibrated out of the system. Integral non-linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code. Differential non-linearity measures the maximum actual code width versus the ideal code width. This measure is unadjusted. The maximum pin leakage current is 1 A. In systems where the device frequency is low, use of the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be 8 s for preferred operation. This is because TAD, when derived from TOSC, is kept away from on-chip phase clock transitions. This reduces, to a large extent, the effects of digital switching noise. This is not possible with the RC derived clock. The loss of accuracy due to digital switching noise can be significant if many I/O pins are active. In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP are stopped. This method gives high accuracy. 13.7 Effects of a RESET Applicable Devices 72 73 73A 74 74A 76 77 A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. For a given range of analog inputs, the output digital code will be the same. This is due to the quantization of the analog input to a digital code. Quantization error is typically 1/2 LSb and is inherent in the analog to digital conversion process. The only way to reduce quantization error is to increase the resolution of the A/D converter. Offset error measures the first actual transition of a code versus the first ideal transition of a code. Offset error shifts the entire transfer function. Offset error can be calibrated out of a system or introduced into a system through the interaction of the total leakage current and source impedance at the analog input. DS30390E-page 124 1997 Microchip Technology Inc. PIC16C7X 13.8 Use of the CCP Trigger FIGURE 13-5: A/D TRANSFER FUNCTION 04h 03h 02h 01h 256 LSb (full scale) 4 LSb 255 LSb 00h 3 LSb An A/D conversion can be started by the "special event trigger" of the CCP2 module (CCP1 on the PIC16C72 only). This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). FFh FEh 2 LSb In the PIC16C72, the "special event trigger" is implemented in the CCP1 module. 0.5 LSb 1 LSb Note: Digital code output Applicable Devices 72 73 73A 74 74A 76 77 Analog input voltage If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter. 13.11 13.9 References Connection Considerations Applicable Devices 72 73 73A 74 74A 76 77 If the input voltage exceeds the rail values (VSS or VDD) by greater than 0.2V, then the accuracy of the conversion is out of specification. A very good reference for understanding A/D converters is the "Analog-Digital Conversion Handbook" third edition, published by Prentice Hall (ISBN 0-13-03-2848-0). An external RC filter is sometimes added for anti-aliasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 k recommended specification. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 13.10 Transfer Function Applicable Devices 72 73 73A 74 74A 76 77 The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage (VAIN) is Analog VREF/256 (Figure 13-5). 1997 Microchip Technology Inc. DS30390E-page 125 PIC16C7X FIGURE 13-6: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes GO = 0? No Yes A/D Clock = RC? SLEEP Yes Instruction? Start of A/D Conversion Delayed 1 Instruction Cycle Finish Conversion GO = 0 ADIF = 1 No No Yes Device in SLEEP? Abort Conversion GO = 0 ADIF = 0 Finish Conversion GO = 0 ADIF = 1 Wake-up Yes From Sleep? Wait 2 TAD No No Finish Conversion GO = 0 ADIF = 1 SLEEP Power-down A/D Stay in Sleep Power-down A/D Wait 2 TAD Wait 2 TAD TABLE 13-2: REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C72 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 -- ADIF -- -- SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 -- ADIE -- -- SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 1Eh ADRES xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON 0000 00-0 0000 00-0 9Fh ADCON1 -- PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 RA0 --0x 0000 --0u 0000 05h PORTA A/D Result Register -- -- -- -- -- RA5 -- RA4 RA3 RA2 RA1 --11 1111 --11 1111 85h TRISA -- -- PORTA Data Direction Register Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. DS30390E-page 126 1997 Microchip Technology Inc. PIC16C7X TABLE 13-3: Address SUMMARY OF A/D REGISTERS, PIC16C73/73A/74/74A/76/77 Name INTCON 0Bh,8Bh, 10Bh,18Bh PIR1 0Ch Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Dh PIR2 -- -- -- -- -- -- -- CCP2IF ---- ---0 ---- ---0 8Dh PIE2 -- -- -- -- -- -- -- CCP2IE ---- ---0 ---- ---0 8Ch 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON 0000 00-0 0000 00-0 9Fh ADCON1 -- -- -- -- -- PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 RA0 --0x 0000 --0u 0000 05h PORTA -- -- 85h TRISA -- -- -- -- RA5 RA4 RA3 PORTA Data Direction Register -- -- -- RA2 RA1 --11 1111 --11 1111 ---- -xxx ---- -uuu RE2 RE1 RE0 09h PORTE -- 0000 -111 89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc. 0000 -111 DS30390E-page 127 PIC16C7X NOTES: DS30390E-page 128 1997 Microchip Technology Inc. PIC16C7X 14.0 SPECIAL FEATURES OF THE CPU Applicable Devices 72 73 73A 74 74A 76 77 What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16CXX family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * Oscillator selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-circuit serial programming the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. 14.1 Configuration Bits Applicable Devices 72 73 73A 74 74A 76 77 The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The PIC16CXX has a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming. FIGURE 14-1: CONFIGURATION WORD FOR PIC16C73/74 -- -- -- -- -- -- -- -- CP1 bit13 CP0 PWRTE WDTE FOSC1 FOSC0 bit0 Register: Address CONFIG 2007h bit 13-5: Unimplemented: Read as '1' bit 4: CP1:CP0: Code protection bits 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 3: PWRTE: Power-up Timer Enable bit 1 = Power-up Timer enabled 0 = Power-up Timer disabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator 1997 Microchip Technology Inc. DS30390E-page 129 PIC16C7X FIGURE 14-2: CONFIGURATION WORD FOR PIC16C72/73A/74A/76/77 CP1 CP0 CP1 CP0 CP1 CP0 -- BODEN CP1 bit13 CP0 PWRTE WDTE FOSC1 FOSC0 bit0 bit 13-8 5-4: CP1:CP0: Code Protection bits (2) 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Register: Address CONFIG 2007h Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. DS30390E-page 130 1997 Microchip Technology Inc. PIC16C7X 14.2 Oscillator Configurations TABLE 14-1: Applicable Devices 72 73 73A 74 74A 76 77 14.2.1 Ranges Tested: Mode OSCILLATOR TYPES XT The PIC16CXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC 14.2.2 Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor FIGURE 14-3: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) XTAL To internal logic RF OSC2 C2 SLEEP PIC16CXX RS Note1 Note 1: A series resistor may be required for AT strip cut crystals. FIGURE 14-4: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) OSC1 PIC16CXX Open HS 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5% All resonators used did not have built-in capacitors. TABLE 14-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Cap. Range C1 Cap. Range C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes at bottom of page. Crystals Used See Table 14-1 and Table 14-2 for recommended values of C1 and C2. Clock from ext. system 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1 Resonators Used: In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 14-3). The PIC16CXX Oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure 14-4). C1 Freq These values are for design guidance only. See notes at bottom of page. CRYSTAL OSCILLATOR/CERAMIC RESONATORS OSC1 CERAMIC RESONATORS OSC2 1997 Microchip Technology Inc. 32 kHz Epson C-001R32.768K-A 20 PPM 200 kHz STD XTL 200.000KHz 20 PPM 1 MHz ECS ECS-10-13-1 50 PPM 4 MHz ECS ECS-40-20-1 50 PPM 8 MHz EPSON CA-301 8.000M-C 30 PPM 20 MHz EPSON CA-301 20.000M-C 30 PPM Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 14-1). 2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. DS30390E-page 131 PIC16C7X 14.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 14-5 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometer biases the 74AS04 in the linear region. This could be used for external oscillator designs. FIGURE 14-5: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT +5V To Other Devices 10k 74AS04 4.7k PIC16CXX CLKIN 74AS04 RC OSCILLATOR For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 14-7 shows how the R/C combination is connected to the PIC16CXX. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g. 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. See characterization data for desired device for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). 10k XTAL 10k 20 pF 14.2.4 20 pF Figure 14-6 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region. See characterization data for desired device for variation of oscillator frequency due to VDD for given Rext/ Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-4 for waveform). FIGURE 14-7: RC OSCILLATOR MODE FIGURE 14-6: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT V DD Rext 330 k 330 k 74AS04 74AS04 0.1 F OSC1 To Other Devices 74AS04 PIC16CXX CLKIN Cext Internal clock PIC16CXX VSS Fosc/4 OSC2/CLKOUT XTAL DS30390E-page 132 1997 Microchip Technology Inc. PIC16C7X 14.3 Reset A simplified block diagram of the on-chip reset circuit is shown in Figure 14-8. Applicable Devices 72 73 73A 74 74A 76 77 The PIC16CXX differentiates between various kinds of reset: * * * * * The PIC16C72/73A/74A/76/77 have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (normal operation) Brown-out Reset (BOR) (PIC16C72/73A/74A/76/ 77) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR reset during SLEEP, and Brownout Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 14-5 and Table 14-6. These bits are used in software to determine the nature of the reset. See Table 14-8 for a full description of reset states of all registers. FIGURE 14-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR SLEEP WDT Time-out Reset WDT Module VDD rise detect VDD Power-on Reset (2) Brown-out Reset S BODEN OST/PWRT OST Chip_Reset R 10-bit Ripple counter Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter Enable PWRT (3) Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: Brown-out Reset is implemented on the PIC16C72/73A/74A/76/77. 3: See Table 14-3 and Table 14-4 for time-out situations. 1997 Microchip Technology Inc. DS30390E-page 133 PIC16C7X 14.4 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST), and Brown-out Reset (BOR) The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. 14.4.3 Applicable Devices 72 73 73A 74 74A 76 77 14.4.1 The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. POWER-ON RESET (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. 14.4.4 When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the startup conditions. BROWN-OUT RESET (BOR) Applicable Devices 72 73 73A 74 74A 76 77 A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for greater than parameter #35, the brown-out situation will reset the chip. A reset may not occur if VDD falls below 4.0V for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will now be invoked and will keep the chip in RESET an additional 72 ms. If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute a 72 ms time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure 14-9 shows typical brown-out situations. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting." 14.4.2 OSCILLATOR START-UP TIMER (OST) POWER-UP TIMER (PWRT) The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. FIGURE 14-9: BROWN-OUT SITUATIONS VDD Internal Reset BVDD Max. BVDD Min. 72 ms VDD Internal Reset BVDD Max. BVDD Min. <72 ms 72 ms VDD Internal Reset DS30390E-page 134 BVDD Max. BVDD Min. 72 ms 1997 Microchip Technology Inc. PIC16C7X 14.4.5 14.4.6 TIME-OUT SEQUENCE On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 14-10, Figure 14-11, and Figure 14-12 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 14-11). This is useful for testing purposes or to synchronize more than one PIC16CXX device operating in parallel. Table 14-7 shows the reset conditions for some special function registers, while Table 14-8 shows the reset conditions for all the registers. TABLE 14-3: Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent resets to see if bit BOR cleared, indicating a BOR occurred. The BOR bit is a "Don't Care" bit and is not necessarily predictable if the Brown-out Reset circuitry is disabled (by clearing bit BODEN in the Configuration Word). Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. Power-up PWRTE = 1 PWRTE = 0 72 ms + 1024TOSC 1024TOSC 72 ms -- XT, HS, LP RC Wake-up from SLEEP 1024 TOSC -- TIME-OUT IN VARIOUS SITUATIONS, PIC16C72/73A/74A/76/77 Oscillator Configuration XT, HS, LP RC TABLE 14-5: The Power Control/Status Register, PCON has up to two bits, depending upon the device. Bit0 is not implemented on the PIC16C73 or PIC16C74. TIME-OUT IN VARIOUS SITUATIONS, PIC16C73/74 Oscillator Configuration TABLE 14-4: POWER CONTROL/STATUS REGISTER (PCON) Applicable Devices 72 73 73A 74 74A 76 77 Power-up PWRTE = 0 PWRTE = 1 72 ms + 1024TOSC 1024TOSC 72 ms -- Brown-out 72 ms + 1024TOSC 72 ms Wake-up from SLEEP 1024TOSC -- STATUS BITS AND THEIR SIGNIFICANCE, PIC16C73/74 POR TO PD 0 0 0 1 1 1 1 1 0 x 0 0 u 1 1 x 0 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP Legend: u = unchanged, x = unknown 1997 Microchip Technology Inc. DS30390E-page 135 PIC16C7X TABLE 14-6: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C72/73A/74A/76/77 POR BOR TO PD 0 0 0 1 1 1 1 1 x x x 0 1 1 1 1 1 0 x x 0 0 u 1 1 x 0 x 1 0 u 0 TABLE 14-7: Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP RESET CONDITION FOR SPECIAL REGISTERS Condition Program Counter STATUS Register PCON Register PCON Register PIC16C73/74 PIC16C72/73A/74A/76/77 Power-on Reset 000h 0001 1xxx ---- --0- ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --u- ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --u- ---- --uu WDT Reset 000h 0000 1uuu ---- --u- ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --u- ---- --uu Brown-out Reset 000h 0001 1uuu N/A ---- --u0 Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --u- ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). TABLE 14-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt W 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu INDF 72 73 73A 74 74A 76 77 N/A N/A N/A TMR0 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PCL 72 73 73A 74 74A 76 77 0000h 0000h PC + 1(2) STATUS 72 73 73A 74 74A 76 77 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTA 72 73 73A 74 74A 76 77 --0x 0000 --0u 0000 --uu uuuu PORTB 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTD 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PORTE 72 73 73A 74 74A 76 77 ---- -xxx ---- -uuu ---- -uuu PCLATH 72 73 73A 74 74A 76 77 ---0 0000 ---0 0000 ---u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-7 for reset value for specific condition. DS30390E-page 136 1997 Microchip Technology Inc. PIC16C7X TABLE 14-8: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.'d) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt 72 73 73A 74 74A 76 77 0000 000x 0000 000u uuuu uuuu(1) 72 73 73A 74 74A 76 77 -0-- 0000 -0-- 0000 -u-- uuuu(1) 72 73 73A 74 74A 76 77 -000 0000 -000 0000 -uuu uuuu(1) 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu(1) PIR2 72 73 73A 74 74A 76 77 ---- ---0 ---- ---0 ---- ---u(1) TMR1L 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 72 73 73A 74 74A 76 77 --00 0000 --uu uuuu --uu uuuu TMR2 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu T2CON 72 73 73A 74 74A 76 77 -000 0000 -000 0000 -uuu uuuu SSPBUF 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu CCPR1L 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 72 73 73A 74 74A 76 77 --00 0000 --00 0000 --uu uuuu RCSTA 72 73 73A 74 74A 76 77 0000 -00x 0000 -00x uuuu -uuu TXREG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu RCREG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu CCPR2L 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu ADRES 72 73 73A 74 74A 76 77 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 72 73 73A 74 74A 76 77 0000 00-0 0000 00-0 uuuu uu-u OPTION 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu TRISA 72 73 73A 74 74A 76 77 --11 1111 --11 1111 --uu uuuu TRISB 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu INTCON PIR1 TRISC 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu TRISD 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu TRISE 72 73 73A 74 74A 76 77 0000 -111 0000 -111 uuuu -uuu 72 73 73A 74 74A 76 77 -0-- 0000 -0-- 0000 -u-- uuuu 72 73 73A 74 74A 76 77 -000 0000 -000 0000 -uuu uuuu 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu 72 73 73A 74 74A 76 77 ---- ---0 ---- ---0 ---- ---u 72 73 73A 74 74A 76 77 ---- --0- ---- --u- ---- --u- 72 73 73A 74 74A 76 77 ---- --0u ---- --uu ---- --uu 72 73 73A 74 74A 76 77 1111 1111 1111 1111 1111 1111 PIE1 PIE2 PCON PR2 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-7 for reset value for specific condition. 1997 Microchip Technology Inc. DS30390E-page 137 PIC16C7X TABLE 14-8: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.'d) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt SSPADD 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu SSPSTAT 72 73 73A 74 74A 76 77 --00 0000 --00 0000 --uu uuuu TXSTA 72 73 73A 74 74A 76 77 0000 -010 0000 -010 uuuu -uuu SPBRG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu ADCON1 72 73 73A 74 74A 76 77 ---- -000 ---- -000 ---- -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-7 for reset value for specific condition. DS30390E-page 138 1997 Microchip Technology Inc. PIC16C7X FIGURE 14-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1997 Microchip Technology Inc. DS30390E-page 139 PIC16C7X FIGURE 14-13: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 14-14: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD D VDD 33k VDD 10k R R1 40k MCLR C MCLR PIC16CXX PIC16CXX Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Note 1: This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal brown-out detection on the PIC16C72/73A/74A/76/77 should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. FIGURE 14-15: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD R1 Q1 MCLR R2 40k PIC16CXX Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 = 0.7V VDD * R1 + R2 2: Internal brown-out detection on the PIC16C72/73A/74A/76/77 should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. DS30390E-page 140 1997 Microchip Technology Inc. PIC16C7X 14.5 Interrupts Applicable Devices 72 73 73A 74 74A 76 77 The PIC16C7X family has up to 12 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset. The "return from interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. For the PIC16C73/74, if an interrupt occurs while the Global Interrupt Enable (GIE) bit is being cleared, the GIE bit may unintentionally be re-enabled by the user's Interrupt Service Routine (the RETFIE instruction). The events that would cause this to occur are: 1. An instruction clears the GIE bit while an interrupt is acknowledged. 2. The program branches to the Interrupt vector and executes the Interrupt Service Routine. 3. The Interrupt Service Routine completes with the execution of the RETFIE instruction. This causes the GIE bit to be set (enables interrupts), and the program returns to the instruction after the one which was meant to disable interrupts. Perform the following to ensure that interrupts are globally disabled: LOOP BCF INTCON, GIE BTFSC INTCON, GIE GOTO : LOOP ; Disable global ; interrupt bit ; Global interrupt ; disabled? ; NO, try again ; Yes, continue ; with program ; flow When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 1417). The latency is the same for one or two cycle 1997 Microchip Technology Inc. DS30390E-page 141 PIC16C7X FIGURE 14-16: INTERRUPT LOGIC PSPIF PSPIE ADIF ADIE Wake-up (If in SLEEP mode) T0IF T0IE RCIF RCIE INTF INTE TXIF TXIE SSPIF SSPIE Interrupt to CPU RBIF RBIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF ADIF PIC16C72 Yes Yes Yes - Yes PIC16C73 Yes Yes Yes - Yes PIC16C73A Yes Yes Yes - Yes PIC16C74 Yes Yes Yes Yes Yes PIC16C74A Yes Yes Yes Yes PIC16C76 Yes Yes Yes PIC16C77 Yes Yes Yes RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF - - Yes Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes FIGURE 14-17: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF flag (INTCON<1>) Interrupt Latency 2 5 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction fetched Inst (PC) Instruction executed Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) 0004h PC+1 -- Dummy Cycle 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. DS30390E-page 142 1997 Microchip Technology Inc. PIC16C7X 14.5.1 14.6 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 14.8 for details on SLEEP mode. Context Saving During Interrupts Applicable Devices 72 73 73A 74 74A 76 77 During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt i.e., W register and STATUS register. This will have to be implemented in software. Example 14-1 stores and restores the STATUS, W, and PCLATH registers. The register, W_TEMP, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). The example: 14.5.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 7.0) 14.5.3 a) b) c) d) e) PORTB INTCON CHANGE f) Stores the W register. Stores the STATUS register in bank 0. Stores the PCLATH register. Executes the ISR code. Restores the STATUS register (and bank select bit). Restores the W and PCLATH registers. An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 5.2) Note: For the PIC16C73/74, if a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. EXAMPLE 14-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF BCF MOVF MOVWF : :(ISR) : MOVF MOVWF SWAPF W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH STATUS, IRP FSR, W FSR_TEMP ;Copy W to TEMP register, could be bank one or zero ;Swap status to be saved into W ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 ;Save status to bank zero STATUS_TEMP register ;Only required if using pages 1, 2 and/or 3 ;Save PCLATH into W ;Page zero, regardless of current page ;Return to Bank 0 ;Copy FSR to W ;Copy FSR from W to FSR_TEMP PCLATH_TEMP, W PCLATH STATUS_TEMP,W MOVWF SWAPF SWAPF STATUS W_TEMP,F W_TEMP,W ;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W 1997 Microchip Technology Inc. DS30390E-page 143 PIC16C7X 14.7 Watchdog Timer (WDT) prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. Applicable Devices 72 73 73A 74 74A 76 77 The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The WDT can be permanently disabled by clearing configuration bit WDTE (Section 14.1). The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. 14.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., and max. WDT prescaler) it may take several seconds before a WDT time-out occurs. Note: 14.7.1 When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a FIGURE 14-18: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 7-6) 0 WDT Timer Postscaler M U X 1 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure 7-6) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION register. FIGURE 14-19: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name 2007h Config. bits 81h,181h OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 14-1, and Figure 14-2 for operation of these bits. DS30390E-page 144 1997 Microchip Technology Inc. PIC16C7X 14.8 Power-down Mode (SLEEP) Applicable Devices 72 73 73A 74 74A 76 77 Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 14.8.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change, or some Peripheral Interrupts. External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). Other peripherals cannot generate interrupts since during SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 14.8.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. 7. 8. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. SSP (Start/Stop) bit detect interrupt. SSP transmit or receive in slave mode (SPI/I2C). CCP capture mode interrupt. Parallel Slave Port read or write. A/D conversion (when A/D clock source is RC). Special event trigger (Timer1 in asynchronous mode using an external clock). USART TX or RX (synchronous slave mode). 1997 Microchip Technology Inc. DS30390E-page 145 PIC16C7X FIGURE 14-20: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 1: 2: 3: 4: 14.9 PC+1 PC+2 Inst(PC + 2) SLEEP Inst(PC + 1) Program Verification/Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. 14.10 Microchip does not recommend code protecting windowed devices. ID Locations Applicable Devices 72 73 73A 74 74A 76 77 Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used. 14.11 PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference. Applicable Devices 72 73 73A 74 74A 76 77 Note: PC+2 Inst(PC + 1) In-Circuit Serial Programming Applicable Devices 72 73 73A 74 74A 76 77 PIC16CXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. DS30390E-page 146 The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Specifications (Literature #DS30228). FIGURE 14-21: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION External Connector Signals To Normal Connections PIC16CXX +5V VDD 0V VSS VPP MCLR/VPP CLK RB6 Data I/O RB7 VDD To Normal Connections 1997 Microchip Technology Inc. PIC16C7X 15.0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. TABLE 15-1: OPCODE FIELD DESCRIPTIONS Field Description Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 label Label name TOS Top of Stack PC Program Counter f W b k x The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 15-2 lists the instructions recognized by the MPASM assembler. Figure 15-1 shows the general formats that the instructions can have. Note: All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. FIGURE 15-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) [ ] ( ) <> Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit Destination either the W register or the specified register file location Options Contents 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) PCLATH Program Counter High Latch GIE WDT TO PD dest To maintain upward compatibility with future PIC16CXX products, do not use the OPTION and TRIS instructions. 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 OPCODE 0 k (literal) k = 8-bit immediate value Assigned to Register bit field In the set of italics User defined term (font is courier) CALL and GOTO instructions only 13 11 OPCODE 10 0 k (literal) k = 11-bit immediate value 1997 Microchip Technology Inc. DS30390E-page 147 PIC16C7X TABLE 15-2: PIC16CXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z Z Z Z Z Z Z Z C C C,DC,Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1,2 1,2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W C,DC,Z Z TO,PD Z TO,PD C,DC,Z Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS30390E-page 148 1997 Microchip Technology Inc. PIC16C7X 15.1 Instruction Descriptions ADDLW Add Literal and W ANDLW AND Literal with W Syntax: [label] ADDLW Syntax: [label] ANDLW Operands: 0 k 255 Operands: 0 k 255 Operation: (W) + k (W) Operation: (W) .AND. (k) (W) C, DC, Z Status Affected: Z Status Affected: Encoding: 11 k 111x kkkk kkkk Encoding: 11 k 1001 kkkk kkkk Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. Description: The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Words: 1 1 Cycles: 1 Cycles: Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W ADDLW 0x15 Q Cycle Activity: Example = = ADDWF Add W and f Syntax: [label] ADDWF Operands: Q3 Q4 Decode Read literal "k" Process data Write to W ANDLW 0x5F W 0x10 = 0xA3 After Instruction After Instruction W Q2 Before Instruction Before Instruction W Q1 W 0x25 = 0x03 ANDWF AND W with f Syntax: [label] ANDWF 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (W) + (f) (destination) Operation: (W) .AND. (f) (destination) Status Affected: C, DC, Z Status Affected: Z Encoding: 00 f,d 0111 dfff ffff Encoding: 00 f,d 0101 dfff ffff Description: Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Description: AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination ADDWF FSR, 0 Before Instruction W = FSR = 1997 Microchip Technology Inc. Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination ANDWF FSR, 1 Before Instruction 0x17 0xC2 After Instruction W = FSR = Q Cycle Activity: W = FSR = 0x17 0xC2 After Instruction 0xD9 0xC2 W = FSR = 0x17 0x02 DS30390E-page 149 PIC16C7X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [label] BCF Syntax: [label] BTFSC f,b Operands: 0 f 127 0b7 Operands: 0 f 127 0b7 Operation: 0 (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff ffff Description: Bit 'b' in register 'f' is cleared. Words: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' BCF Encoding: 10bb bfff ffff Description: Words: 1 Cycles: 1(2) Q Cycle Activity: FLAG_REG, 7 01 If bit 'b' in register 'f' is '1' then the next instruction is executed. If bit 'b', in register 'f', is '0' then the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction. Before Instruction Q1 Q2 Q3 Q4 Decode Read register 'f' Process data NoOperation Q3 Q4 FLAG_REG = 0xC7 If Skip: After Instruction FLAG_REG = 0x47 Example (2nd Cycle) Q1 Q2 NoOperation NoOperation HERE FALSE TRUE BTFSC GOTO * * * NoNoOperation Operation FLAG,1 PROCESS_CODE Before Instruction PC = address HERE After Instruction BSF Bit Set f Syntax: [label] BSF Operands: 0 f 127 0b7 Operation: 1 (f<b>) Status Affected: None Encoding: 01 if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE f,b 01bb bfff Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Q Cycle Activity: Example ffff Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A DS30390E-page 150 1997 Microchip Technology Inc. PIC16C7X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 f 127 0b<7 Operands: 0 k 2047 Operation: Operation: skip if (f<b>) = 1 Status Affected: None (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Status Affected: None Encoding: Description: 01 1 Cycles: 1(2) If Skip: Example bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction. Words: Q Cycle Activity: 11bb Q1 Q2 Q3 Q4 Decode Read register 'f' Process data NoOperation (2nd Cycle) Q1 Q2 NoOperation NoOperation HERE FALSE TRUE BTFSC GOTO * * * Q3 10 FLAG,1 PROCESS_CODE kkkk kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k', Push PC to Stack Process data Write to PC Q4 NoNoOperation Operation 0kkk Description: 1st Cycle 2nd Cycle Example NoNoNoNoOperation Operation Operation Operation HERE CALL THERE Before Instruction PC = Address HERE After Instruction Before Instruction PC = Encoding: address HERE PC = Address THERE TOS = Address HERE+1 After Instruction if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE 1997 Microchip Technology Inc. DS30390E-page 151 PIC16C7X CLRF Clear f Syntax: [label] CLRF Operands: 0 f 127 Operation: 00h (f) 1Z Status Affected: Z Encoding: 00 f 0001 1fff ffff CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h (W) 1Z Status Affected: Z Encoding: 00 0001 0xxx xxxx Description: The contents of register 'f' are cleared and the Z bit is set. Description: W register is cleared. Zero bit (Z) is set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' CLRF Q Cycle Activity: Example FLAG_REG = 0x5A Q3 Q4 NoOperation Process data Write to W CLRW = = 0x00 1 W = 0x5A After Instruction After Instruction FLAG_REG Z Q2 Before Instruction Before Instruction FLAG_REG Q1 Decode W Z = = 0x00 1 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Encoding: 00 0000 0110 0100 Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. Words: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode NoOperation Process data Clear WDT Counter CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = WDT prescaler= TO = PD = DS30390E-page 152 0x00 0 1 1 1997 Microchip Technology Inc. PIC16C7X COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF Syntax: [ label ] DECFSZ f,d Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) (destination) Operation: Status Affected: Z (f) - 1 (destination); skip if result = 0 Status Affected: None Encoding: Description: 00 f,d 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Encoding: COMF 0x13 1 Cycles: 1(2) = = 0x13 0xEC If Skip: After Instruction REG1 W DECF Decrement f Syntax: [label] DECF f,d Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Encoding: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Q3 Q4 NoNoNoOperation Operation Operation Example 0011 dfff ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example HERE DECFSZ GOTO CONTINUE * * * Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination DECF NoOperation CNT, 1 LOOP Before Instruction Description: Q Cycle Activity: (2nd Cycle) Q1 Q2 PC 00 ffff Words: Before Instruction = dfff The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 1, the next instruction, is executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruction. REG1,0 REG1 1011 Description: Q Cycle Activity: Example 00 = address HERE After Instruction CNT if CNT PC if CNT PC = = = = CNT - 1 0, address CONTINUE 0, address HERE+1 CNT, 1 Before Instruction CNT Z = = 0x01 0 = = 0x00 1 After Instruction CNT Z 1997 Microchip Technology Inc. DS30390E-page 153 PIC16C7X GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 2047 Operands: Operation: k PC<10:0> PCLATH<4:3> PC<12:11> 0 f 127 d [0,1] Operation: (f) + 1 (destination) None Status Affected: Z Status Affected: Encoding: 10 GOTO k 1kkk kkkk kkkk Encoding: 00 INCF f,d 1010 dfff ffff Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction. Description: The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Words: 1 Cycles: 2 Cycles: 1 Q Cycle Activity: 1st Cycle 2nd Cycle Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to PC Q Cycle Activity: Q2 Q3 Q4 Read register 'f' Process data Write to destination INCF CNT, 1 NoNoNoNoOperation Operation Operation Operation Example Example Q1 Decode Before Instruction GOTO THERE After Instruction PC = Address THERE CNT Z 0xFF 0 = = 0x00 1 After Instruction CNT Z DS30390E-page 154 = = 1997 Microchip Technology Inc. PIC16C7X INCFSZ Increment f, Skip if 0 Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Encoding: Description: 00 1 Cycles: 1(2) If Skip: 1111 dfff Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Q3 Q4 NoNoNoOperation Operation Operation Example ffff Q1 (2nd Cycle) Q1 Q2 HERE INCFSZ GOTO CONTINUE * * * Inclusive OR Literal with W Syntax: [ label ] Operands: 0 k 255 Operation: (W) .OR. k (W) Status Affected: Z Encoding: The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead making it a 2TCY instruction. Words: Q Cycle Activity: INCFSZ f,d IORLW 11 IORLW k 1000 kkkk kkkk Description: The contents of the W register is OR'ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W IORLW 0x35 Before Instruction W = 0x9A After Instruction W Z = = 0xBF 1 NoOperation CNT, 1 LOOP Before Instruction PC = address HERE After Instruction CNT = if CNT= PC = if CNT PC = 1997 Microchip Technology Inc. CNT + 1 0, address CONTINUE 0, address HERE +1 DS30390E-page 155 PIC16C7X IORWF Inclusive OR W with f MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: (W) .OR. (f) (destination) Operation: k (W) Status Affected: Z Status Affected: None Encoding: IORWF 00 f,d 0100 dfff ffff Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Example Encoding: 11 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination IORWF 00xx kkkk kkkk Description: The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's. Words: 1 Cycles: 1 Q Cycle Activity: Q1 MOVLW k Example Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W MOVLW 0x5A After Instruction RESULT, 0 W = 0x5A Before Instruction RESULT = W = 0x13 0x91 After Instruction RESULT = W = Z = 0x13 0x93 1 MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Encoding: Encoding: Description: 00 1 Cycles: 1 Example 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: Q Cycle Activity: MOVF f,d Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination MOVF FSR, 0 After Instruction MOVWF Move W to f Syntax: [ label ] Operands: 0 f 127 Operation: (W) (f) Status Affected: None 00 MOVWF 0000 f 1fff ffff Description: Move data from W register to register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' MOVWF OPTION_REG Before Instruction OPTION = W = 0xFF 0x4F After Instruction OPTION = W = 0x4F 0x4F W = value in FSR register Z =1 DS30390E-page 156 1997 Microchip Technology Inc. PIC16C7X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS PC, 1 GIE Status Affected: None Encoding: 00 NOP 0000 0xx0 0000 RETFIE Description: No operation. Encoding: Words: 1 Description: Cycles: 1 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode Example Q2 Q3 Q4 NoNoNoOperation Operation Operation NOP Q Cycle Activity: 1st Cycle 2nd Cycle Example 00 0000 0000 1001 Q1 Q2 Q3 Q4 Decode NoOperation Set the GIE bit Pop from the Stack NoNoNoNoOperation Operation Operation Operation RETFIE After Interrupt PC = GIE = OPTION Load Option Register Syntax: [ label ] Operands: None Operation: (W) OPTION TOS 1 OPTION Status Affected: None Encoding: 00 0000 0110 0010 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction. 1997 Microchip Technology Inc. DS30390E-page 157 PIC16C7X RETLW Return with Literal in W RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: None Operation: k (W); TOS PC Operation: TOS PC Status Affected: None Status Affected: None Encoding: RETLW k Encoding: 11 Description: 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: 1st Cycle 2nd Cycle Q2 Decode Read literal 'k' Q3 Q4 NoWrite to W, Operation Pop from the Stack NoNoNoNoOperation Operation Operation Operation 0000 0000 1000 Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 00 RETURN 1st Cycle 2nd Cycle Example Q1 Decode Q2 Q3 Q4 NoNoPop from Operation Operation the Stack NoNoNoNoOperation Operation Operation Operation RETURN After Interrupt Example CALL TABLE ;W contains table ;offset value ;W now has table value * * * TABLE ADDWF PC RETLW k1 RETLW k2 PC = TOS ;W = offset ;Begin table ; * * * RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W DS30390E-page 158 = value of k8 1997 Microchip Technology Inc. PIC16C7X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: Description: RLF 00 f,d 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. C Encoding: Description: 00 Register f Words: 1 Cycles: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination RLF REG1,0 1997 Microchip Technology Inc. ffff Register f Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination RRF REG1,0 Before Instruction = = 1110 0110 0 = = = 1110 0110 1100 1100 1 After Instruction REG1 W C Q Cycle Activity: Example Before Instruction REG1 C dfff C 1 Example 1100 The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: Q Cycle Activity: RRF f,d REG1 C = = 1110 0110 0 = = = 1110 0110 0111 0011 0 After Instruction REG1 W C DS30390E-page 159 PIC16C7X SLEEP SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Operation: k - (W) (W) Status Affected: C, DC, Z SLEEP Encoding: 11 110x kkkk kkkk Description: The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register. The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 14.8 for more details. Words: 1 Cycles: 1 Words: 1 Example 1: Cycles: 1 Status Affected: TO, PD Encoding: Description: Q Cycle Activity: 00 0000 0110 0011 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W SUBLW 0x02 Before Instruction Q1 Decode Q2 Q3 NoNoOperation Operation Q4 W C Z Go to Sleep = = = 1 ? ? After Instruction Example: SLEEP W C Z Example 2: = = = 1 1; result is positive 0 Before Instruction W C Z = = = 2 ? ? After Instruction W C Z Example 3: = = = 0 1; result is zero 1 Before Instruction W C Z = = = 3 ? ? After Instruction W C Z DS30390E-page 160 = = = 0xFF 0; result is negative 0 1997 Microchip Technology Inc. PIC16C7X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] SWAPF f,d Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - (W) (destination) Operation: Status Affected: C, DC, Z (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None Encoding: Description: 00 1 Cycles: 1 Example 1: 0010 dfff ffff Subtract (2's complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: Q Cycle Activity: SUBWF f,d Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination SUBWF Encoding: 00 REG1 W C Z ffff Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Example = = = = SWAPF REG, REG1 W C Z = = = = REG1 = = = = = = = = 2 2 ? ? = = = = 1997 Microchip Technology Inc. = = = = 0xA5 0x5A Load TRIS Register Syntax: [label] Operands: 5f7 Operation: (W) TRIS register f; TRIS f Status Affected: None 0 2 1; result is zero 1 1 2 ? ? After Instruction REG1 W C Z = = TRIS Encoding: 0xFF 2 0; result is negative 0 00 0000 0110 0fff Description: The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them. Words: 1 Cycles: 1 Before Instruction REG1 W C Z 0xA5 1 2 1; result is positive 0 After Instruction REG1 W C Z = After Instruction REG1 W Before Instruction REG1 W C Z 0 Before Instruction 3 2 ? ? After Instruction Example 3: dfff The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. REG1,1 Before Instruction Example 2: 1110 Description: Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction. DS30390E-page 161 PIC16C7X XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] Syntax: [label] Operands: 0 k 255 Operands: Operation: (W) .XOR. k (W) 0 f 127 d [0,1] Status Affected: Z Operation: (W) .XOR. (f) (destination) Status Affected: Z Encoding: 11 XORLW k 1010 kkkk kkkk Description: The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W XORLW Encoding: 00 XORWF 0110 f,d dfff ffff Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination 0xAF Before Instruction W = Example 0xB5 After Instruction W = 0x1A XORWF REG 1 Before Instruction REG W = = 0xAF 0xB5 = = 0x1A 0xB5 After Instruction REG W DS30390E-page 162 1997 Microchip Technology Inc. PIC16C7X 16.0 DEVELOPMENT SUPPORT 16.1 Development Tools The PIC16/17 microcontrollers are supported with a full range of hardware and software development tools: * PICMASTER/PICMASTER CE Real-Time In-Circuit Emulator * ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE II Universal Programmer * PICSTART Plus Entry-Level Prototype Programmer * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLAB-SIM Software Simulator * MPLAB-C (C Compiler) * Fuzzy logic development system (fuzzyTECH-MP) 16.2 PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE 16.3 ICEPIC: Low-cost PIC16CXXX In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT through Pentium based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation. 16.4 PRO MATE II: Universal Programmer The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC16C5X, PIC16CXXX, PIC17CXX and PIC14000 devices. It can also set configuration and code-protect bits in this mode. The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC12C5XX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. 16.5 Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers. PICSTART Plus supports all PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket. PICSTART Plus Entry Level Development System The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows 3.x environment were chosen to best make these features available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries. 1997 Microchip Technology Inc. DS30390E-page 163 PIC16C7X 16.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-16B programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB. 16.7 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-16C, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad. 16.8 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include DS30390E-page 164 an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. 16.9 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PIC16/17 tools (automatically updates all project information) * Debug using: - source files - absolute listing file * Transfer data dynamically via DDE (soon to be replaced by OLE) * Run up to four emulators on the same PC The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 16.10 Assembler (MPASM) The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from PICMASTER, Microchip's Universal Emulator System. 1997 Microchip Technology Inc. PIC16C7X MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PIC16/17. Directives are helpful in making the development of your assemble source code shorter and more maintainable. 16.11 Software Simulator (MPLAB-SIM) The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16/17 series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 16.12 C Compiler (MPLAB-C) The MPLAB-C Code Development System is a complete `C' compiler and integrated development environment for Microchip's PIC16/17 family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display (PICMASTER emulator software versions 1.13 and later). 16.13 16.14 MP-DriveWay - Application Code Generator MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually configure all the peripherals in a PIC16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip's MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation. 16.15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system. 16.16 TrueGauge Intelligent Battery Management The TrueGauge development tool supports system development with the MTA11200B TrueGauge Intelligent Battery Management IC. System design verification can be accomplished before hardware prototypes are built. User interface is graphically-oriented and measured data can be saved in a file for exporting to Microsoft Excel. 16.17 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters. Fuzzy Logic Development System (fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for implementing more complex systems. Both versions include Microchip's fuzzyLAB demonstration board for hands-on experience with fuzzy logic systems implementation. 1997 Microchip Technology Inc. DS30390E-page 165 Emulator Products Software Tools DS30390E-page 166 Programmers KEELOQ Evaluation Kit PICDEM-3 PICDEM-2 PICDEM-1 SEEVAL Designers Kit KEELOQ Programmer PRO MATE II Universal Programmer PICSTART Plus Low-Cost Universal Dev. Kit PICSTART Lite Ultra Low-Cost Dev. Kit Total Endurance Software Model fuzzyTECH-MP Explorer/Edition Fuzzy Logic Dev. Tool MP-DriveWay Applications Code Generator MPLAB C Compiler MPLAB Integrated Development Environment ICEPIC Low-Cost In-Circuit Emulator PICMASTER/ PICMASTER-CE In-Circuit Emulator PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X Available 3Q97 PIC17C75X 24CXX 25CXX 93CXX HCS200 HCS300 HCS301 TABLE 16-1: Demo Boards PIC12C5XX PIC16C7X DEVELOPMENT TOOLS FROM MICROCHIP 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.0 ELECTRICAL CHARACTERISTICS FOR PIC16C72 Absolute Maximum Ratings Ambient temperature under bias..................................................................................................................-55 to +125C Storage temperature ............................................................................................................................... -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2) ................................................................................................. 0 to +14V Voltage on RA4 with respect to Vss ................................................................................................................... 0 to +14V Total power dissipation (Note 1).................................................................................................................................1.0W Maximum current out of VSS pin ............................................................................................................................300 mA Maximum current into VDD pin ...............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) ..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. 20 mA Maximum output current sunk by any I/O pin...........................................................................................................25 mA Maximum output current sourced by any I/O pin .....................................................................................................25 mA Maximum current sunk by PORTA and PORTB (combined)..................................................................................200 mA Maximum current sourced by PORTA and PORTB (combined).............................................................................200 mA Maximum current sunk by PORTC ........................................................................................................................200 mA Maximum current sourced by PORTC ...................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 17-1: OSC CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C72-04 PIC16C72-10 PIC16C72-20 PIC16LC72-04 JW Devices RC VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. XT VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. HS LP VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Not recommended for use in LP mode Not recommended for use in LP mode VDD: 4.5V to 5.5V IDD: 20 mA max. at 5.5V Not recommended for use in HS mode IPD: 1.5 A typ. at 4.5V VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. Freq: 20 MHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. 1997 Microchip Technology Inc. DS30390E-page 167 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.1 DC Characteristics: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions D001 D001A Supply Voltage VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VDD start voltage to ensure internal Poweron Reset Signal VPOR - VSS - V D004* VDD rise rate to ensure internal Power-on Reset Signal SVDD 0.05 - - D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled 3.7 4.0 4.4 V Extended Only - 2.7 5.0 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) - 10 20 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D010 Supply Current (Note 2,5) IDD D013 XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details D015 Brown-out Reset Current IBOR (Note 6) - 350 425 A BOR enabled VDD = 5.0V D020 D021 D021A D021B Power-down Current (Note 3,5) - 10.5 1.5 1.5 2.5 42 16 19 19 A A A A VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +125C D023 Brown-out Reset Current IBOR (Note 6) - 350 425 A BOR enabled VDD = 5.0V * Note 1: 2: 3: 4: 5: 6: IPD These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30390E-page 168 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.2 DC Characteristics: PIC16LC72-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions 2.5 - 6.0 V RAM Data Retention Volt- VDR age (Note 1) - 1.5 - V D003 VPOR VDD start voltage to ensure internal Power-on Reset signal - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - 3.7 4.0 4.3 V - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled - 350 425 A BOR enabled VDD = 5.0V - 7.5 0.9 0.9 30 5 5 A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C - 350 425 A BOR enabled VDD = 5.0V D001 Supply Voltage D002* VDD D005 Brown-out Reset Voltage BVDD D010 Supply Current (Note 2,5) IDD D010A D015* Brown-out Reset Current IBOR (Note 6) D020 Power-down Current D021 (Note 3,5) D021A D023* * Note 1: 2: 3: 4: 5: 6: IPD Brown-out Reset Current IBOR (Note 6) LP, XT, RC osc configuration (DC - 4 MHz) See section on Power-on Reset for details V/ms See section on Power-on Reset for details BODEN bit in configuration word enabled These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 1997 Microchip Technology Inc. DS30390E-page 169 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.3 DC Characteristics: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) PIC16LC72-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. D030 D030A D031 D032 D033 D040 D040A D041 D042 D042A D043 D070 Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 17.1 and Section 17.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VSS VIH 2.0 0.25VDD + 0.8V D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current IPURB Input Leakage Current (Notes 2, 3) I/O ports IIL D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D080A D083 OSC2/CLKOUT (RC osc config) D083A VOL - 0.15VDD 0.8V - 0.2VDD - 0.2VDD - 0.3VDD V V V V V For entire VDD range 4.5 VDD 5.5V - VDD VDD V V 4.5 VDD 5.5V For entire VDD range VDD VDD VDD VDD 400 V For entire VDD range V V Note1 V A VDD = 5V, VPIN = VSS 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 250 - - 1 - - 5 5 - - 0.6 V - - 0.6 V - - 0.6 V - - 0.6 V Note1 A Vss VPIN VDD, Pin at hiimpedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30390E-page 170 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 17.1 and Section 17.2. Sym Min Typ Max Units Conditions VOH VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V D090A D092 OSC2/CLKOUT (RC osc config) D092A D150* D100 Open-Drain High Voltage VOD Capacitive Loading Specs on Output Pins OSC2 pin COSC2 - - 14 V - - 15 pF IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1. D101 D102 All I/O pins and OSC2 (in RC mode) CIO 50 pF 400 pF CB SCL, SDA in I2C mode * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. DS30390E-page 171 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 17-1: LOAD CONDITIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin VSS CL Pin VSS RL = 464 CL = 50 pF 15 pF DS30390E-page 172 for all pins except OSC2 for OSC2 output 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17.5 Timing Diagrams and Specifications FIGURE 17-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 17-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Fosc External CLKIN Frequency (Note 1) Min Typ Max Units Conditions DC -- 4 MHz XT and RC osc mode DC -- 4 MHz HS osc mode (-04) DC -- 10 MHz HS osc mode (-10) DC -- 20 MHz HS osc mode (-20) DC -- 200 kHz LP osc mode Oscillator Frequency DC -- 4 MHz RC osc mode (Note 1) 0.1 -- 4 MHz XT osc mode 4 -- 20 MHz HS osc mode 5 -- 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 -- -- ns XT and RC osc mode (Note 1) 250 -- -- ns HS osc mode (-04) 100 -- -- ns HS osc mode (-10) 50 -- -- ns HS osc mode (-20) 5 -- -- s LP osc mode Oscillator Period 250 -- -- ns RC osc mode (Note 1) 250 -- 10,000 ns XT osc mode 250 -- 250 ns HS osc mode (-04) 100 -- 250 ns HS osc mode (-10) 50 -- 250 ns HS osc mode (-20) 5 -- -- s LP osc mode 200 -- DC ns TCY = 4/FOSC 2 TCY Instruction Cycle Time (Note 1) 3 TosL, External Clock in (OSC1) High or 100 -- -- ns XT oscillator TosH Low Time 2.5 -- -- s LP oscillator 15 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or -- -- 25 ns XT oscillator TosF Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1997 Microchip Technology Inc. DS30390E-page 173 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 17-1 for load conditions. TABLE 17-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No. Characteristic Min Typ Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT -- 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT -- 75 200 ns Note 1 12* TckR CLKOUT rise time -- 35 100 ns Note 1 13* TckF CLKOUT fall time -- 35 100 ns Note 1 14* TckL2ioV CLKOUT to Port out valid -- -- 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT TOSC + 200 -- -- ns Note 1 16* TckH2ioI Port in hold after CLKOUT 0 -- -- ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid -- 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) PIC16C72 100 -- -- ns PIC16LC72 200 -- -- ns 19* TioV2osH Port input valid to OSC1 (I/O in setup time) 0 -- -- ns 20* TioR Port output rise time PIC16C72 -- 10 40 ns PIC16LC72 -- -- 80 ns PIC16C72 -- 10 40 ns PIC16LC72 -- -- 80 ns 21* TioF Port output fall time 22* Tinp INT pin high or low time TCY -- -- ns 23* Trbp RB7:RB4 change INT high or low time TCY -- -- ns * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30390E-page 174 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 17-1 for load conditions. FIGURE 17-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No. Sym Characteristic 30 TmcL MCLR Pulse Width (low) 2 -- -- s VDD = 5V, -40C to +125C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40C to +125C * 32 Tost 33* Tpwrt 34 35 Min Typ Max Units Conditions Oscillation Start-up Timer Period -- 1024TOSC -- -- TOSC = OSC1 period Power-up Timer Period 28 72 132 ms VDD = 5V, -40C to +125C TIOZ I/O Hi-impedance from MCLR Low or Watchdog Timer Reset -- -- 2.1 s TBOR Brown-out Reset pulse width 100 -- -- s VDD BVDD (D005) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 175 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 17-1 for load conditions. TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * Tt0L Min Typ Max 0.5TCY + 20 -- -- ns 10 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns 0.5TCY + 20 10 Tt0P T0CKI Period TCY + 40 No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C7X 15 Prescaler = PIC16LC7X 25 2,4,8 Asynchronous PIC16C7X 30 PIC16LC7X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C7X 15 Prescaler = PIC16LC7X 25 2,4,8 Asynchronous PIC16C7X 30 PIC16LC7X 50 Tt1P T1CKI input period Synchronous PIC16C7X Greater of: 30 OR TCY + 40 N Greater of: PIC16LC7X 50 OR TCY + 40 N Asynchronous PIC16C7X 60 PIC16LC7X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Units Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) -- -- -- -- -- 200 ns ns kHz -- 7Tosc -- These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 176 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 17-1 for load conditions. TABLE 17-6: Param No. 50* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Sym Characteristic TccL CCP1 input low time Min No Prescaler With Prescaler PIC16C72 PIC16LC72 51* TccH CCP1 input high time No Prescaler With Prescaler PIC16C72 PIC16LC72 52* TccP CCP1 input period 53* TccR CCP1 output rise time 54* * TccF CCP1 output fall time Typ Max Units Conditions 0.5TCY + 20 -- -- ns 10 -- -- ns 20 -- -- ns 0.5TCY + 20 -- -- ns 10 -- -- ns 20 -- -- ns 3TCY + 40 N -- -- ns PIC16C72 -- 10 25 ns PIC16LC72 -- 25 45 ns PIC16C72 -- 10 25 ns PIC16LC72 -- 25 45 ns N = prescale value (1,4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 177 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 17-1 for load conditions TABLE 17-7: SPI MODE REQUIREMENTS Parameter No. Sym Characteristic Min Typ Max Units TCY -- -- ns 70 TssL2scH, TssL2scL SS to SCK or SCK input 71 TscH SCK input high time (slave mode) TCY + 20 -- -- ns 72 TscL SCK input low time (slave mode) TCY + 20 -- -- ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 50 -- -- ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 50 -- -- ns 75 TdoR SDO data output rise time -- 10 25 ns 76 TdoF SDO data output fall time -- 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 -- 50 ns 78 TscR SCK output rise time (master mode) -- 10 25 ns 79 TscF SCK output fall time (master mode) -- 10 25 ns Conditions 80 TscH2doV, SDO data output valid after SCK -- -- 50 ns TscL2doV edge Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 178 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-9: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 17-1 for load conditions TABLE 17-8: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90 TSU:STA 91 THD:STA 92 TSU:STO 93 THD:STO Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 1997 Microchip Technology Inc. Min 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4700 600 4000 600 4700 600 4000 600 Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns DS30390E-page 179 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-10: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 17-1 for load conditions I2C BUS DATA REQUIREMENTS TABLE 17-9: Parameter No. Sym Characteristic 100 THIGH Clock high time 101 102 103 TLOW TR TF Clock low time SDA and SCL rise time SDA and SCL fall time 90 TSU:STA START condition setup time 91 THD:STA START condition hold time 106 THD:DAT Data input hold time 107 TSU:DAT Data input setup time 92 TSU:STO STOP condition setup time 109 TAA Output valid from clock 110 TBUF Bus free time Cb Bus capacitive loading Min Max Units Conditions 100 kHz mode 4.0 -- s 400 kHz mode 0.6 -- s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz SSP Module 100 kHz mode 1.5TCY 4.7 -- -- s 400 kHz mode 1.3 -- s SSP Module 100 kHz mode 400 kHz mode 1.5TCY -- 20 + 0.1Cb -- 1000 300 ns ns 100 kHz mode 400 kHz mode -- 20 + 0.1Cb 300 300 ns ns 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- s s s s ns s ns ns s s ns ns s s -- 400 pF Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Only relevant for repeated START condition After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz)S I2C-bus system, but the requirement tsu;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. DS30390E-page 180 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 17-10: A/D CONVERTER CHARACTERISTICS: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) PIC16LC72-04 (Commercial, Industrial) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ Max Units Conditions -- -- 8-bits bit -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF A03 EIL A04 EDL Differential linearity error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A05 EFS Full scale error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A06 EOFF Offset error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A10 -- Integral linearity error Min VSS VAIN VREF Monotonicity -- guaranteed -- -- A20 VREF Reference voltage 3.0V -- VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 -- VREF + 0.3 V A30 ZAIN Recommended impedance of analog voltage source -- -- 10.0 k A40 IAD PIC16C72 -- 180 -- A PIC16LC72 -- 90 -- A 10 -- 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 13.1. -- -- 10 A During A/D Conversion cycle A50 A/D conversion current (VDD) IREF VREF input current (Note 2) Average current consumption when A/D is on. (Note 1) * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 1997 Microchip Technology Inc. DS30390E-page 181 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17-11: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 17-11: A/D CONVERSION REQUIREMENTS Param No. 130 Sym Characteristic TAD A/D clock period Units Conditions 1.6 -- -- s 2.0 -- -- s TOSC based, VREF full range PIC16C72 2.0 4.0 6.0 s A/D RC Mode PIC16LC72 3.0 6.0 9.0 s A/D RC Mode -- 9.5 -- TAD Note 2 20 -- s 5* -- -- s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). -- TOSC/2 -- -- If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1.5 -- -- TAD 132 TACQ Acquisition time Q4 to A/D clock start TSWC Switching from convert sample time 135 Max PIC16C72 TCNV Conversion time (not including S/H time) (Note 1) TGO Typ PIC16LC72 131 134 Min TOSC based, VREF 3.0V * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 13.1 for min conditions. DS30390E-page 182 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73/74 Absolute Maximum Ratings Ambient temperature under bias..................................................................................................................-55 to +125C Storage temperature ............................................................................................................................... -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)...........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2) ................................................................................................. 0 to +14V Voltage on RA4 with respect to Vss ................................................................................................................... 0 to +14V Total power dissipation (Note 1).................................................................................................................................1.0W Maximum current out of VSS pin ............................................................................................................................300 mA Maximum current into VDD pin ...............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) ..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. 20 mA Maximum output current sunk by any I/O pin...........................................................................................................25 mA Maximum output current sourced by any I/O pin .....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3).....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ...............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3) ...................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3)..............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE are not implemented on the PIC16C73. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 18-1: OSC CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C73-04 PIC16C74-04 PIC16C73-10 PIC16C74-10 PIC16C73-20 PIC16C74-20 PIC16LC73-04 PIC16LC74-04 JW Devices RC VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 3.0V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 13.5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. XT VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 3.0V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 13.5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 15 mA max. at 5.5V IDD: 30 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. HS LP VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Not recommended for use in LP mode Not recommended for use in LP mode VDD: 4.5V to 5.5V Not recommended for use in HS mode IDD: 30 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 3.0V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 13.5 A max. at 3.0V Freq: 200 kHz max. VDD: 3.0V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 13.5 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. 1997 Microchip Technology Inc. DS30390E-page 183 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.1 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VPOR VDD start voltage to ensure internal Power-on Reset signal - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal 0.05 - - D010 Supply Current (Note 2,5) IDD - 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V - 10.5 1.5 1.5 42 21 24 A A A VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C SVDD D013 D020 Power-down Current D021 (Note 3,5) D021A * Note 1: 2: 3: 4: 5: IPD XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. DS30390E-page 184 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.2 DC Characteristics: PIC16LC73/74-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions D001 Supply Voltage VDD 3.0 - 6.0 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VPOR VDD start voltage to ensure internal Power-on Reset signal - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal 0.05 - - D010 Supply Current (Note 2,5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled - 7.5 0.9 0.9 30 13.5 18 A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C SVDD D010A D020 D021 D021A * Note 1: 2: 3: 4: 5: Power-down Current (Note 3,5) IPD LP, XT, RC osc configuration (DC - 4 MHz) See section on Power-on Reset for details V/ms See section on Power-on Reset for details These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 1997 Microchip Technology Inc. DS30390E-page 185 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.3 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) PIC16LC73/74-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Characteristic Input Low Voltage I/O ports with TTL buffer D030 D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP) Input High Voltage I/O ports D040 with TTL buffer D040A D041 D042 D042A D043 D070 D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D083 OSC2/CLKOUT (RC osc config) D090 Output High Voltage I/O ports (Note 3) D092 OSC2/CLKOUT (RC osc config) D150* * Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 18.1 and Section 18.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VSS VIH 2.0 0.25VDD + 0.8V - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5V VDD 5.5V - VDD VDD V V 4.5V VDD 5.5V For entire VDD range VDD VDD VDD VDD 400 V For entire VDD range V V Note1 V A VDD = 5V, VPIN = VSS 0.8VDD 0.8VDD 0.7VDD 0.9VDD IPURB 50 250 - - 1 - - 5 5 - - 0.6 V - - 0.6 V VOH VDD - 0.7 - - V VDD - 0.7 - - V IIL VOL Note1 A Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin Open-Drain High Voltage VOD 14 V These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30390E-page 186 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 DC CHARACTERISTICS Param No. D100 Characteristic Capacitive Loading Specs on Output Pins OSC2 pin Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 18.1 and Section 18.2. Sym Min Typ Max Units Conditions COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 D102 All I/O pins and OSC2 (in RC CIO 50 pF 400 pF CB mode) SCL, SDA in I2C mode * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. DS30390E-page 187 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 18-1: LOAD CONDITIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin VSS CL Pin VSS RL = 464 CL = 50 pF 15 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C73. DS30390E-page 188 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.5 Timing Diagrams and Specifications FIGURE 18-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 18-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Fosc External CLKIN Frequency (Note 1) Min Typ Max Units Conditions DC -- 4 MHz XT and RC osc mode DC -- 4 MHz HS osc mode (-04) DC -- 10 MHz HS osc mode (-10) DC -- 20 MHz HS osc mode (-20) DC -- 200 kHz LP osc mode Oscillator Frequency DC -- 4 MHz RC osc mode (Note 1) 0.1 -- 4 MHz XT osc mode 4 -- 20 MHz HS osc mode 5 -- 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 -- -- ns XT and RC osc mode (Note 1) 250 -- -- ns HS osc mode (-04) 100 -- -- ns HS osc mode (-10) 50 -- -- ns HS osc mode (-20) 5 -- -- s LP osc mode Oscillator Period 250 -- -- ns RC osc mode (Note 1) 250 -- 10,000 ns XT osc mode 250 -- 250 ns HS osc mode (-04) 100 -- 250 ns HS osc mode (-10) 50 -- 250 ns HS osc mode (-20) 5 -- -- s LP osc mode 200 -- DC ns TCY = 4/FOSC 2 TCY Instruction Cycle Time (Note 1) 3 TosL, External Clock in (OSC1) High or 50 -- -- ns XT oscillator TosH Low Time 2.5 -- -- s LP oscillator 15 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or -- -- 25 ns XT oscillator TosF Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1997 Microchip Technology Inc. DS30390E-page 189 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 18-1 for load conditions. TABLE 18-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No. Characteristic Min Typ Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT -- 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT -- 75 200 ns Note 1 12* TckR CLKOUT rise time -- 35 100 ns Note 1 13* TckF CLKOUT fall time -- 35 100 ns Note 1 14* TckL2ioV CLKOUT to Port out valid -- -- 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT 0.25TCY + 25 -- -- ns Note 1 16* TckH2ioI Port in hold after CLKOUT 0 -- -- ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid -- 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) PIC16C73/74 100 -- -- ns PIC16LC73/74 200 -- -- ns 19* TioV2osH Port input valid to OSC1 (I/O in setup time) 0 -- -- ns 20* TioR Port output rise time PIC16C73/74 -- 10 25 ns PIC16LC73/74 -- -- 60 ns PIC16C73/74 -- 10 25 ns PIC16LC73/74 -- -- 60 ns 21* TioF Port output fall time 22* Tinp INT pin high or low time TCY -- -- ns 23* Trbp RB7:RB4 change INT high or low time TCY -- -- ns * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30390E-page 190 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 18-1 for load conditions. TABLE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No. Sym Characteristic Min 30 TmcL MCLR Pulse Width (low) 100 -- -- ns VDD = 5V, -40C to +85C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40C to +85C * 32 Tost 33* Tpwrt 34 TIOZ Typ Max Units Conditions Oscillation Start-up Timer Period -- 1024TOSC -- -- TOSC = OSC1 period Power up Timer Period 28 72 132 ms VDD = 5V, -40C to +85C I/O Hi-impedance from MCLR Low or Watchdog Timer Reset -- -- 100 ns These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 191 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 18-1 for load conditions. TABLE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * Tt0L Min Typ Max 0.5TCY + 20 -- -- ns 10 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns 0.5TCY + 20 10 Tt0P T0CKI Period TCY + 40 No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C7X 15 Prescaler = PIC16LC7X 25 2,4,8 Asynchronous PIC16C7X 30 PIC16LC7X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C7X 15 Prescaler = PIC16LC7X 25 2,4,8 Asynchronous PIC16C7X 30 PIC16LC7X 50 Tt1P T1CKI input period Synchronous PIC16C7X Greater of: 30 OR TCY + 40 N Greater of: PIC16LC7X 50 OR TCY + 40 N Asynchronous PIC16C7X 60 PIC16LC7X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Units Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) -- -- -- -- -- 200 ns ns kHz -- 7Tosc -- These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 192 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 18-1 for load conditions. TABLE 18-6: Parameter No. 50* 51* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym Characteristic TccL CCP1 and CCP2 input low time TccH CCP1 and CCP2 input high time Min No Prescaler * -- -- ns 10 -- -- ns 20 -- -- ns 0.5TCY + 20 -- -- ns PIC16C73/74 10 -- -- ns PIC16LC73/74 20 -- -- ns 3TCY + 40 N -- -- ns No Prescaler 52* TccP CCP1 and CCP2 input period 53* TccR CCP1 and CCP2 output fall time 54* 0.5TCY + 20 PIC16C73/74 With Prescaler PIC16LC73/74 With Prescaler TccF CCP1 and CCP2 output fall time Typ Max Units Conditions PIC16C73/74 -- 10 25 ns PIC16LC73/74 -- 25 45 ns PIC16C73/74 -- 10 25 ns PIC16LC73/74 -- 25 45 ns N = prescale value (1,4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 193 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-7: PARALLEL SLAVE PORT TIMING (PIC16C74) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 18-1 for load conditions TABLE 18-7: Parameter No. * PARALLEL SLAVE PORT REQUIREMENTS (PIC16C74) Sym Characteristic 62 TdtV2wrH Data in valid before WR or CS (setup time) 63* TwrH2dtI WR or CS to data-in invalid (hold time) Min Typ Max Units 20 -- -- Conditions ns PIC16C74 20 -- -- ns PIC16LC74 35 -- -- ns 64 TrdL2dtV RD and CS to data-out valid -- -- 80 ns 65 TrdH2dtI RD or CS to data-out invalid 10 -- 30 ns These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 194 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 18-1 for load conditions TABLE 18-8: Parameter No. SPI MODE REQUIREMENTS Sym Characteristic Min Typ Max Units TCY -- -- ns 70 TssL2scH, TssL2scL SS to SCK or SCK input 71 TscH SCK input high time (slave mode) TCY + 20 -- -- ns 72 TscL SCK input low time (slave mode) TCY + 20 -- -- ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 50 -- -- ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 50 -- -- ns 75 TdoR SDO data output rise time -- 10 25 ns 76 TdoF SDO data output fall time -- 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 -- 50 ns 78 TscR SCK output rise time (master mode) -- 10 25 ns 79 TscF SCK output fall time (master mode) -- 10 25 ns Conditions 80 TscH2doV, SDO data output valid after SCK -- -- 50 ns TscL2doV edge Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 195 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-9: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 18-1 for load conditions TABLE 18-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90 TSU:STA 91 THD:STA 92 TSU:STO 93 THD:STO DS30390E-page 196 Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time Min 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4700 600 4000 600 4700 600 4000 600 Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-10: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 18-1 for load conditions TABLE 18-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100 THIGH Clock high time 101 102 103 TLOW TR TF Clock low time SDA and SCL rise time SDA and SCL fall time 90 TSU:STA START condition setup time 91 THD:STA START condition hold time 106 THD:DAT Data input hold time 107 TSU:DAT Data input setup time 92 TSU:STO STOP condition setup time 109 TAA Output valid from clock 110 TBUF Bus free time Min Max Units Conditions 100 kHz mode 4.0 -- s 400 kHz mode 0.6 -- s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz SSP Module 100 kHz mode 1.5TCY 4.7 -- -- s 400 kHz mode 1.3 -- s SSP Module 100 kHz mode 400 kHz mode 1.5TCY -- 20 + 0.1Cb -- 1000 300 ns ns 100 kHz mode 400 kHz mode -- 20 + 0.1Cb 300 300 ns ns 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- s s s s ns s ns ns s s ns ns s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Only relevant for repeated START condition After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Cb Bus capacitive loading -- 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. 1997 Microchip Technology Inc. DS30390E-page 197 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 18-1 for load conditions TABLE 18-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter No. 120 121 Characteristic TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid Tckrf 122 : Sym Tdtrf Min Clock out rise time and fall time (Master Mode) Data out rise time and fall time Typ Max Units Conditions PIC16C73/74 -- -- 80 ns PIC16LC73/74 -- -- 100 ns PIC16C73/74 -- -- 45 ns PIC16LC73/74 -- -- 50 ns PIC16C73/74 -- -- 45 ns PIC16LC73/74 -- -- 50 ns Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 18-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 18-1 for load conditions TABLE 18-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter No. : Sym Characteristic Min Typ Max 125 TdtV2ckL 126 TckL2dtl Units Conditions SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) 15 -- -- ns Data hold after CK (DT hold time) 15 -- -- ns Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 198 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 18-13: A/D CONVERTER CHARACTERISTICS: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) PIC16LC73/74-04 (Commercial, Industrial) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ Max Units Conditions -- -- 8-bits bit -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF A03 EIL A04 EDL Differential linearity error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A05 EFS Full scale error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A06 EOFF Offset error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A10 -- Integral linearity error Min VSS VAIN VREF Monotonicity -- guaranteed -- -- A20 VREF Reference voltage 3.0V -- VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 -- VREF + 0.3 V A30 ZAIN Recommended impedance of analog voltage source -- -- 10.0 k A40 IAD PIC16C73/74 -- 180 -- A PIC16LC73/74 -- 90 -- A 10 -- 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 13.1. -- -- 10 A During A/D Conversion cycle A50 A/D conversion current (VDD) IREF VREF input current (Note 2) Average current consumption when A/D is on. (Note 1) * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 1997 Microchip Technology Inc. DS30390E-page 199 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18-13: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 18-14: A/D CONVERSION REQUIREMENTS Param No. 130 Sym Characteristic TAD A/D clock period Min Typ Max Units Conditions PIC16C73/74 1.6 -- -- s PIC16LC73/74 2.0 -- -- s TOSC based, VREF 3.0V TOSC based, VREF full range PIC16C73/74 2.0 4.0 6.0 s A/D RC Mode A/D RC Mode PIC16LC73/74 3.0 6.0 9.0 s 131 TCNV Conversion time (not including S/H time) (Note 1) -- 9.5 -- TAD 132 TACQ Acquisition time Note 2 20 -- s 5* -- -- s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). -- TOSC/2 -- -- If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1.5 -- -- TAD 134 TGO Q4 to A/D clock start TSWC Switching from convert sample time 135 * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 13.1 for min conditions. DS30390E-page 200 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73A/74A Absolute Maximum Ratings Ambient temperature under bias..................................................................................................................-55 to +125C Storage temperature ............................................................................................................................... -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)...........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2) ................................................................................................. 0 to +14V Voltage on RA4 with respect to Vss ................................................................................................................... 0 to +14V Total power dissipation (Note 1).................................................................................................................................1.0W Maximum current out of VSS pin ............................................................................................................................300 mA Maximum current into VDD pin ...............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) ..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. 20 mA Maximum output current sunk by any I/O pin...........................................................................................................25 mA Maximum output current sourced by any I/O pin .....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3).....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ...............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3) ...................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3)..............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE are not implemented on the PIC16C73A. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 19-1: OSC CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C73A-04 PIC16C74A-04 PIC16C73A-10 PIC16C74A-10 PIC16C73A-20 PIC16C74A-20 PIC16LC73A-04 PIC16LC74A-04 JW Devices RC VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. XT VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. HS LP VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Not recommended for use in LP mode Not recommended for use in LP mode VDD: 4.5V to 5.5V Not recommended for use in HS mode IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. 1997 Microchip Technology Inc. DS30390E-page 201 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.1 DC Characteristics: PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VPOR VDD start voltage to ensure internal Power-on Reset signal - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled 3.7 4.0 4.4 V Extended Range Only - 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) - 10 20 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V IBOR - 350 425 A BOR enabled VDD = 5.0V D020 Power-down Current D021 (Note 3,5) D021A D021B IPD - 10.5 1.5 1.5 2.5 42 16 19 19 A A A A VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +125C D023* IBOR - 350 425 A BOR enabled VDD = 5.0V D010 Supply Current (Note 2,5) IDD D013 D015* * Note 1: 2: 3: 4: 5: 6: Brown-out Reset Current (Note 6) Brown-out Reset Current (Note 6) XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30390E-page 202 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.2 DC Characteristics: PIC16LC73A/74A-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions D001 Supply Voltage VDD 2.5 - 6.0 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VPOR VDD start voltage to ensure internal Power-on Reset signal - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V D010 Supply Current (Note 2,5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D010A LP, XT, RC osc configuration (DC - 4 MHz) See section on Power-on Reset for details V/ms See section on Power-on Reset for details BODEN bit in configuration word enabled D015* Brown-out Reset Current IBOR (Note 6) - 350 425 A BOR enabled VDD = 5.0V D020 D021 D021A Power-down Current (Note 3,5) - 7.5 0.9 0.9 30 5 5 A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C D023* Brown-out Reset Current IBOR (Note 6) - 350 425 A BOR enabled VDD = 5.0V * Note 1: 2: 3: 4: 5: 6: IPD These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 1997 Microchip Technology Inc. DS30390E-page 203 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.3 DC Characteristics: PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) PIC16LC73A/74A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Characteristic Input Low Voltage I/O ports with TTL buffer D030 D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP) Input High Voltage I/O ports D040 with TTL buffer D040A D041 D042 D042A D043 D070 D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D080A D083 OSC2/CLKOUT (RC osc config) D083A Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 19.1 and Section 19.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VSS VIH 2.0 0.25VDD + 0.8V - 0.15VDD 0.8V - 0.2VDD - 0.2VDD - 0.3VDD - 0.8VDD 0.8VDD 0.7VDD 0.9VDD IPURB 50 250 IIL VOL V For entire VDD range 4.5V VDD 5.5V V V V Note1 VDD VDD V V 4.5V VDD 5.5V For entire VDD range VDD VDD VDD VDD 400 V For entire VDD range V V Note1 V A VDD = 5V, VPIN = VSS - - 1 A Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration - - 5 5 - - 0.6 V - - 0.6 V - - 0.6 V - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30390E-page 204 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 19.1 and Section 19.2. Sym Min Typ Max Units Conditions VOH VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V D090A D092 OSC2/CLKOUT (RC osc config) D092A D150* D100 Open-Drain High Voltage Capacitive Loading Specs on Output Pins OSC2 pin VOD - - 14 V COSC2 - - 15 pF IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1. D101 D102 All I/O pins and OSC2 (in RC CIO 50 pF 2 400 pF C B mode) SCL, SDA in I C mode * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. DS30390E-page 205 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 19-1: LOAD CONDITIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 CL = 50 pF 15 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C73A. DS30390E-page 206 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19.5 Timing Diagrams and Specifications FIGURE 19-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 19-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Fosc External CLKIN Frequency (Note 1) Min Typ Max Units Conditions DC -- 4 MHz XT and RC osc mode DC -- 4 MHz HS osc mode (-04) DC -- 10 MHz HS osc mode (-10) DC -- 20 MHz HS osc mode (-20) DC -- 200 kHz LP osc mode Oscillator Frequency DC -- 4 MHz RC osc mode (Note 1) 0.1 -- 4 MHz XT osc mode 4 -- 20 MHz HS osc mode 5 -- 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 -- -- ns XT and RC osc mode (Note 1) 250 -- -- ns HS osc mode (-04) 100 -- -- ns HS osc mode (-10) 50 -- -- ns HS osc mode (-20) 5 -- -- s LP osc mode Oscillator Period 250 -- -- ns RC osc mode (Note 1) 250 -- 10,000 ns XT osc mode 250 -- 250 ns HS osc mode (-04) 100 -- 250 ns HS osc mode (-10) 50 -- 250 ns HS osc mode (-20) 5 -- -- s LP osc mode 200 TCY DC ns TCY = 4/FOSC 2 TCY Instruction Cycle Time (Note 1) 3 TosL, External Clock in (OSC1) High or 100 -- -- ns XT oscillator TosH Low Time 2.5 -- -- s LP oscillator 15 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or -- -- 25 ns XT oscillator TosF Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1997 Microchip Technology Inc. DS30390E-page 207 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 19-1 for load conditions. TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym No. Characteristic Min Typ Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT -- 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT -- 75 200 ns Note 1 12* TckR CLKOUT rise time -- 35 100 ns Note 1 13* TckF CLKOUT fall time -- 35 100 ns Note 1 14* TckL2ioV CLKOUT to Port out valid -- -- 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT TOSC + 200 -- -- ns Note 1 16* TckH2ioI Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid 18* TosH2ioI Port in hold after CLKOUT OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) 0 -- -- ns -- 50 150 ns PIC16C73A/74A 100 -- -- ns PIC16LC73A/74A 200 -- -- ns 19* TioV2osH Port input valid to OSC1 (I/O in setup time) 0 -- -- ns 20* TioR PIC16C73A/74A -- 10 40 ns PIC16LC73A/74A -- -- 80 ns PIC16C73A/74A -- 10 40 ns PIC16LC73A/74A -- -- 80 ns 21* TioF Port output rise time Port output fall time 22* Tinp INT pin high or low time TCY -- -- ns 23* Trbp RB7:RB4 change INT high or low time TCY -- -- ns * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30390E-page 208 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 19-1 for load conditions. FIGURE 19-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No. Sym Characteristic 30 TmcL MCLR Pulse Width (low) 2 -- -- s VDD = 5V, -40C to +125C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40C to +125C * 32 Tost 33* Tpwrt 34 35 Min Typ Max Units Conditions Oscillation Start-up Timer Period -- 1024TOSC -- -- TOSC = OSC1 period Power up Timer Period 28 72 132 ms VDD = 5V, -40C to +125C TIOZ I/O Hi-impedance from MCLR Low or Watchdog Timer Reset -- -- 2.1 s TBOR Brown-out Reset pulse width 100 -- -- s VDD BVDD (D005) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 209 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 19-1 for load conditions. TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * Tt0L Min Typ Max 0.5TCY + 20 -- -- ns 10 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns 0.5TCY + 20 10 Tt0P T0CKI Period TCY + 40 No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C7X 15 Prescaler = PIC16LC7X 25 2,4,8 Asynchronous PIC16C7X 30 PIC16LC7X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C7X 15 Prescaler = PIC16LC7X 25 2,4,8 Asynchronous PIC16C7X 30 PIC16LC7X 50 Tt1P T1CKI input period Synchronous PIC16C7X Greater of: 30 OR TCY + 40 N Greater of: PIC16LC7X 50 OR TCY + 40 N Asynchronous PIC16C7X 60 PIC16LC7X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Units Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) -- -- -- -- -- 200 ns ns kHz -- 7Tosc -- These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 210 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 19-1 for load conditions. TABLE 19-6: Param No. 50* 51* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym Characteristic TccL CCP1 and CCP2 input low time TccH CCP1 and CCP2 input high time Min No Prescaler -- -- ns 10 -- -- ns 20 -- -- ns 0.5TCY + 20 -- -- ns PIC16C73A/74A 10 -- -- ns PIC16LC73A/74A 20 -- -- ns 3TCY + 40 N -- -- ns -- 10 25 ns No Prescaler 52* TccP CCP1 and CCP2 input period 53* TccR CCP1 and CCP2 output rise time 54* TccF CCP1 and CCP2 output fall time * 0.5TCY + 20 PIC16C73A/74A With Prescaler PIC16LC73A/74A With Prescaler Typ Max Units Conditions PIC16C73A/74A PIC16LC73A/74A -- 25 45 ns PIC16C73A/74A -- 10 25 ns PIC16LC73A/74A -- 25 45 ns N = prescale value (1,4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 211 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-8: PARALLEL SLAVE PORT TIMING (PIC16C74A) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 19-1 for load conditions TABLE 19-7: Parameter No. 62 PARALLEL SLAVE PORT REQUIREMENTS (PIC16C74A) Sym Characteristic Min Typ Max Units TdtV2wrH Data in valid before WR or CS (setup time) 63* TwrH2dtI WR or CS to data-in invalid (hold time) PIC16C74A PIC16LC74A 64 65 * TrdL2dtV TrdH2dtI RD and CS to data-out valid RD or CS to data-out invalid 20 25 -- -- -- -- ns ns 20 -- -- ns 35 -- -- ns -- -- -- -- 80 90 ns ns 10 -- 30 ns Conditions Extended Range Only Extended Range Only These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 212 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 19-1 for load conditions TABLE 19-8: Parameter No. SPI MODE REQUIREMENTS Sym Characteristic Min Typ Max Units TCY -- -- ns -- -- ns 70 TssL2scH, TssL2scL SS to SCK or SCK input 71 TscH SCK input high time (slave mode) TCY + 20 72 TscL SCK input low time (slave mode) TCY + 20 -- -- ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 100 -- -- ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 -- -- ns 75 TdoR SDO data output rise time -- 10 25 ns 76 TdoF SDO data output fall time -- 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 -- 50 ns 78 TscR SCK output rise time (master mode) -- 10 25 ns 79 TscF SCK output fall time (master mode) -- 10 25 ns Conditions 80 TscH2doV, SDO data output valid after SCK -- -- 50 ns TscL2doV edge Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 213 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-10: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 19-1 for load conditions TABLE 19-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90 TSU:STA 91 THD:STA 92 TSU:STO 93 THD:STO DS30390E-page 214 Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time Min 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4700 600 4000 600 4700 600 4000 600 Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-11: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 19-1 for load conditions TABLE 19-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100 THIGH Clock high time 101 102 103 TLOW TR TF Clock low time SDA and SCL rise time SDA and SCL fall time 90 TSU:STA START condition setup time 91 THD:STA START condition hold time 106 THD:DAT Data input hold time 107 TSU:DAT Data input setup time 92 TSU:STO STOP condition setup time 109 TAA Output valid from clock 110 TBUF Bus free time Min Max Units Conditions 100 kHz mode 4.0 -- s 400 kHz mode 0.6 -- s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz SSP Module 100 kHz mode 1.5TCY 4.7 -- -- s 400 kHz mode 1.3 -- s SSP Module 100 kHz mode 400 kHz mode 1.5TCY -- 20 + 0.1Cb -- 1000 300 ns ns 100 kHz mode 400 kHz mode -- 20 + 0.1Cb 300 300 ns ns 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- s s s s ns s ns ns s s ns ns s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Only relevant for repeated START condition After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Cb Bus capacitive loading -- 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. 1997 Microchip Technology Inc. DS30390E-page 215 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 19-1 for load conditions TABLE 19-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. 120 121 Characteristic TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid Tckrf 122 : Sym Tdtrf Min Typ Max Units Conditions PIC16C73A/74A -- -- 80 ns PIC16LC73A/74A -- -- 100 ns Clock out rise time and fall time PIC16C73A/74A (Master Mode) PIC16LC73A/74A -- -- 45 ns -- -- 50 ns Data out rise time and fall time PIC16C73A/74A -- -- 45 ns PIC16LC73A/74A -- -- 50 ns Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 19-13: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 19-1 for load conditions TABLE 19-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter No. : Sym Characteristic Min Typ Max 125 TdtV2ckL 126 TckL2dtl Units Conditions SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) 15 -- -- ns Data hold after CK (DT hold time) 15 -- -- ns Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 216 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 19-13: A/D CONVERTER CHARACTERISTICS: PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) PIC16LC73A/74A-04 (Commercial, Industrial) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ Max Units Conditions -- -- 8-bits bit -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF A03 EIL A04 EDL Differential linearity error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A05 EFS Full scale error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A06 EOFF Offset error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A10 -- Integral linearity error Min Monotonicity -- guaranteed -- -- A20 VREF Reference voltage 3.0V -- VDD + 0.3 V VSS VAIN VREF A25 VAIN Analog input voltage VSS - 0.3 -- VREF + 0.3 V A30 ZAIN Recommended impedance of analog voltage source -- -- 10.0 k A40 IAD PIC16C73A/74A -- 180 -- A PIC16LC73A/74A -- 90 -- A 10 -- 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 13.1. -- -- 10 A During A/D Conversion cycle A50 A/D conversion current (VDD) IREF VREF input current (Note 2) Average current consumption when A/D is on. (Note 1) * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 1997 Microchip Technology Inc. DS30390E-page 217 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19-14: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2) (1) 131 Q4 130 132 A/D CLK 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 19-14: A/D CONVERSION REQUIREMENTS Param No. 130 Sym Characteristic TAD A/D clock period Min Typ Max Units Conditions PIC16C73A/74A 1.6 -- -- s PIC16LC73A/74A 2.0 -- -- s TOSC based, VREF 3.0V TOSC based, VREF full range PIC16C73A/74A 2.0 4.0 6.0 s A/D RC Mode A/D RC Mode PIC16LC73A/74A 3.0 6.0 9.0 s 131 TCNV Conversion time (not including S/H time) (Note 1) -- 9.5 -- TAD 132 TACQ Acquisition time Note 2 20 -- s 5* -- -- s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). -- TOSC/2 -- -- If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1.5 -- -- TAD 134 TGO Q4 to A/D clock start TSWC Switching from convert sample time 135 * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 13.1 for min conditions. DS30390E-page 218 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.0 ELECTRICAL CHARACTERISTICS FOR PIC16C76/77 Absolute Maximum Ratings Ambient temperature under bias..................................................................................................................-55 to +125C Storage temperature ............................................................................................................................... -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4)...........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2) ................................................................................................. 0 to +14V Voltage on RA4 with respect to Vss ................................................................................................................... 0 to +14V Total power dissipation (Note 1).................................................................................................................................1.0W Maximum current out of VSS pin ............................................................................................................................300 mA Maximum current into VDD pin ...............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) ..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................. 20 mA Maximum output current sunk by any I/O pin...........................................................................................................25 mA Maximum output current sourced by any I/O pin .....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3).....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ...............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3) ...................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3)..............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE are not implemented on the PIC16C76. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1997 Microchip Technology Inc. DS30390E-page 219 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20-1: OSC RC XT CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C76-04 PIC16C77-04 VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. PIC16C76-10 PIC16C77-10 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. PIC16C76-20 PIC16C77-20 VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. PIC16LC76-04 PIC16LC77-04 VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5 A max. at 3V Freq: 4 MHz max. JW Devices VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. IDD: 10 mA max. IDD: 20 mA max. IDD: 20 mA max. at 5.5V at 5.5V at 5.5V at 5.5V Not recommended for HS use in HS mode IPD: 1.5 A typ. IPD: 1.5 A typ. IPD: 1.5 A typ. IPD: 1.5 A typ. at 4.5V at 4.5V at 4.5V at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 52.5 A typ. IDD: 48 A max. IDD: 48 A max. at 32 kHz, 4.0V Not recommended for Not recommended for at 32 kHz, 3.0V at 32 kHz, 3.0V LP IPD: 0.9 A typ. use in LP mode use in LP mode IPD: 5.0 A max. IPD: 5.0 A max. at 4.0V at 3.0V at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. DS30390E-page 220 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.1 DC Characteristics: PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VPOR VDD start voltage to ensure internal Power-on Reset signal - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled 3.7 4.0 4.4 V Extended Range Only - 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) - 10 20 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V IBOR - 350 425 A BOR enabled VDD = 5.0V D020 Power-down Current D021 (Note 3,5) D021A D021B IPD - 10.5 1.5 1.5 2.5 42 16 19 19 A A A A VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +125C D023* IBOR - 350 425 A BOR enabled VDD = 5.0V D010 Supply Current (Note 2,5) IDD D013 D015* * Note 1: 2: 3: 4: 5: 6: Brown-out Reset Current (Note 6) Brown-out Reset Current (Note 6) XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 1997 Microchip Technology Inc. DS30390E-page 221 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.2 DC Characteristics: PIC16LC76/77-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions D001 Supply Voltage VDD 2.5 - 6.0 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VPOR VDD start voltage to ensure internal Power-on Reset signal - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V D010 Supply Current (Note 2,5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D010A LP, XT, RC osc configuration (DC - 4 MHz) See section on Power-on Reset for details V/ms See section on Power-on Reset for details BODEN bit in configuration word enabled D015* Brown-out Reset Current IBOR (Note 6) - 350 425 A BOR enabled VDD = 5.0V D020 D021 D021A Power-down Current (Note 3,5) - 7.5 0.9 0.9 30 5 5 A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C D023* Brown-out Reset Current IBOR (Note 6) - 350 425 A BOR enabled VDD = 5.0V * Note 1: 2: 3: 4: 5: 6: IPD These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30390E-page 222 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.3 DC Characteristics: PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) PIC16LC76/77-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Characteristic Input Low Voltage I/O ports with TTL buffer D030 D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP) Input High Voltage I/O ports D040 with TTL buffer D040A D041 D042 D042A D043 D070 D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D080A D083 OSC2/CLKOUT (RC osc config) D083A Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 20.1 and Section 20.2. Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VSS VIH 2.0 0.25VDD + 0.8V - 0.15VDD 0.8V - 0.2VDD - 0.2VDD - 0.3VDD V V V V V For entire VDD range 4.5V VDD 5.5V - VDD VDD V V 4.5V VDD 5.5V For entire VDD range VDD VDD VDD VDD 400 V For entire VDD range V V Note1 V A VDD = 5V, VPIN = VSS 0.8VDD 0.8VDD 0.7VDD 0.9VDD IPURB 50 250 IIL VOL - - 1 - - 5 5 - - 0.6 V - - 0.6 V - - 0.6 V - - 0.6 V Note1 A Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. DS30390E-page 223 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended, -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Section 20.1 and Section 20.2. Sym Min Typ Max Units Conditions VOH VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V VDD - 0.7 - - V D090A D092 OSC2/CLKOUT (RC osc config) D092A D150* D100 Open-Drain High Voltage Capacitive Loading Specs on Output Pins OSC2 pin VOD - - 14 V COSC2 - - 15 pF IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1. D101 D102 All I/O pins and OSC2 (in RC CIO 50 pF 2 400 pF CB mode) SCL, SDA in I C mode * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30390E-page 224 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 20-1: LOAD CONDITIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 CL = 50 pF 15 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C76. 1997 Microchip Technology Inc. DS30390E-page 225 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20.5 Timing Diagrams and Specifications FIGURE 20-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 20-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Typ Max Fosc External CLKIN Frequency (Note 1) DC DC DC DC DC DC 0.1 4 5 250 250 100 50 5 250 250 250 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 4 10 20 200 4 4 20 200 -- -- -- -- -- -- 10,000 250 250 Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) Units Conditions MHz MHz MHz MHz kHz MHz MHz MHz kHz ns ns ns ns s ns ns ns ns XT and RC osc mode HS osc mode (-04) HS osc mode (-10) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode XT and RC osc mode HS osc mode (-04) HS osc mode (-10) HS osc mode (-20) LP osc mode RC osc mode XT osc mode HS osc mode (-04) HS osc mode (-10) HS osc mode (-20) 50 -- 250 ns 5 -- -- s LP osc mode 200 TCY DC ns TCY = 4/FOSC 2 TCY Instruction Cycle Time (Note 1) 3 TosL, External Clock in (OSC1) High or 100 -- -- ns XT oscillator TosH Low Time 2.5 -- -- s LP oscillator 15 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or -- -- 25 ns XT oscillator TosF Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. DS30390E-page 226 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 20-1 for load conditions. TABLE 20-3: Param Sym No. CLKOUT AND I/O TIMING REQUIREMENTS Characteristic Min Typ Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT -- 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT -- 75 200 ns Note 1 12* TckR CLKOUT rise time -- 35 100 ns Note 1 13* TckF CLKOUT fall time -- 35 100 ns Note 1 14* TckL2ioV CLKOUT to Port out valid -- -- 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT 16* TckH2ioI 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid 18* TosH2ioI TOSC + 200 -- -- ns Note 1 0 -- -- ns Note 1 -- 50 150 ns PIC16C76/77 100 -- -- ns PIC16LC76/77 200 -- -- ns Port in hold after CLKOUT OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) 19* TioV2osH Port input valid to OSC1 (I/O in setup time) 0 -- -- ns 20* TioR Port output rise time -- 10 40 ns 21* TioF Port output fall time 22* Tinp INT pin high or low time 23* Trbp RB7:RB4 change INT high or low time TCY PIC16C76/77 PIC16LC76/77 -- -- 80 ns PIC16C76/77 -- 10 40 ns -- -- 80 ns TCY -- -- ns -- -- ns PIC16LC76/77 * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 1997 Microchip Technology Inc. DS30390E-page 227 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 20-1 for load conditions. FIGURE 20-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No. Sym Characteristic Min Typ Max Units 30 TmcL 31* MCLR Pulse Width (low) 2 -- -- s VDD = 5V, -40C to +125C Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40C to +125C 32 Tost Oscillation Start-up Timer Period -- 1024TOSC -- -- TOSC = OSC1 period 33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40C to +125C 34 TIOZ I/O Hi-impedance from MCLR Low or Watchdog Timer Reset -- -- 2.1 s TBOR Brown-out Reset pulse width 100 -- -- s 35 * Conditions VDD BVDD (D005) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 228 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 20-1 for load conditions. TABLE 20-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * Tt0L Min Typ Max 0.5TCY + 20 -- -- ns 10 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns 0.5TCY + 20 10 Tt0P T0CKI Period TCY + 40 No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C7X 15 Prescaler = PIC16LC7X 25 2,4,8 Asynchronous PIC16C7X 30 PIC16LC7X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C7X 15 Prescaler = PIC16LC7X 25 2,4,8 Asynchronous PIC16C7X 30 PIC16LC7X 50 Tt1P T1CKI input period Synchronous PIC16C7X Greater of: 30 OR TCY + 40 N Greater of: PIC16LC7X 50 OR TCY + 40 N Asynchronous PIC16C7X 60 PIC16LC7X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Units Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) -- -- -- -- -- 200 ns ns kHz -- 7Tosc -- These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 229 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 20-1 for load conditions. TABLE 20-6: Param No. 50* 51* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym Characteristic TccL CCP1 and CCP2 input low time TccH CCP1 and CCP2 input high time Min No Prescaler PIC16C76/77 With Prescaler PIC16LC76/77 52* TccP CCP1 and CCP2 input period 53* TccR CCP1 and CCP2 output rise time 54* TccF CCP1 and CCP2 output fall time -- -- ns 10 -- -- ns 20 -- -- ns 0.5TCY + 20 -- -- ns PIC16C76/77 10 -- -- ns PIC16LC76/77 20 -- -- ns 3TCY + 40 N -- -- ns PIC16C76/77 -- 10 25 ns PIC16LC76/77 -- 25 45 ns PIC16C76/77 -- 10 25 ns PIC16LC76/77 -- 25 45 ns No Prescaler With Prescaler * 0.5TCY + 20 Typ Max Units Conditions N = prescale value (1,4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 230 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-8: PARALLEL SLAVE PORT TIMING (PIC16C77) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 20-1 for load conditions TABLE 20-7: Parameter No. 62 PARALLEL SLAVE PORT REQUIREMENTS (PIC16C77) Sym Characteristic Min Typ Max Units TdtV2wrH Data in valid before WR or CS (setup time) 63* TwrH2dtI WR or CS to data-in invalid (hold time) PIC16C77 PIC16LC77 64 65 * TrdL2dtV TrdH2dtI RD and CS to data-out valid RD or CS to data-out invalid 20 25 -- -- -- -- ns ns 20 -- -- ns 35 -- -- ns -- -- -- -- 80 90 ns ns 10 -- 30 ns Conditions Extended Range Only Extended Range Only These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 231 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-9: SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSB SDO LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 20-1 for load conditions. FIGURE 20-10: SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 BIT6 - - - - - -1 MSB SDO LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 Refer to Figure 20-1 for load conditions. DS30390E-page 232 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-11: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSB SDO LSB BIT6 - - - - - -1 77 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 20-1 for load conditions. FIGURE 20-12: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSB SDO BIT6 - - - - - -1 LSB 75, 76 SDI MSB IN 77 BIT6 - - - -1 LSB IN 74 Refer to Figure 20-1 for load conditions. 1997 Microchip Technology Inc. DS30390E-page 233 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20-8: Parameter No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* SPI MODE REQUIREMENTS Sym TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscH2doV, TscL2doV TdoV2scH, TdoV2scL TssL2doV 83* * Characteristic Min Typ Max Units SS to SCK or SCK input TCY -- -- ns -- -- -- -- -- -- ns ns ns -- -- ns 10 10 -- 10 10 -- 25 25 50 25 25 50 ns ns ns ns ns ns -- -- ns -- 50 ns SCK input high time (slave mode) TCY + 20 SCK input low time (slave mode) TCY + 20 Setup time of SDI data input to SCK 100 edge Hold time of SDI data input to SCK 100 edge SDO data output rise time -- SDO data output fall time -- SS to SDO output hi-impedance 10 SCK output rise time (master mode) -- SCK output fall time (master mode) -- SDO data output valid after SCK -- edge SDO data output setup to SCK TCY edge SDO data output valid after SS -- edge SS after SCK edge 1.5TCY + 40 Conditions TscH2ssH, -- -- ns TscL2ssH These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 234 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-13: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 20-1 for load conditions TABLE 20-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90 TSU:STA 91 THD:STA 92 TSU:STO 93 THD:STO Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 1997 Microchip Technology Inc. Min 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4700 600 4000 600 4700 600 4000 600 Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns DS30390E-page 235 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-14: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 20-1 for load conditions TABLE 20-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100 THIGH Clock high time 101 102 103 TLOW TR TF Clock low time SDA and SCL rise time SDA and SCL fall time 90 TSU:STA START condition setup time 91 THD:STA START condition hold time 106 THD:DAT Data input hold time 107 TSU:DAT Data input setup time 92 TSU:STO STOP condition setup time 109 TAA Output valid from clock 110 TBUF Bus free time Min Max Units Conditions 100 kHz mode 4.0 -- s 400 kHz mode 0.6 -- s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz SSP Module 100 kHz mode 1.5TCY 4.7 -- -- s 400 kHz mode 1.3 -- s SSP Module 100 kHz mode 400 kHz mode 1.5TCY -- 20 + 0.1Cb -- 1000 300 ns ns 100 kHz mode 400 kHz mode -- 20 + 0.1Cb 300 300 ns ns 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- s s s s ns s ns ns s s ns ns s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Only relevant for repeated START condition After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Cb Bus capacitive loading -- 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. DS30390E-page 236 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 20-1 for load conditions TABLE 20-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. 120 121 Characteristic TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid Tckrf 122 : Sym Tdtrf Min Typ Max Units Conditions PIC16C76/77 -- -- 80 ns PIC16LC76/77 -- -- 100 ns Clock out rise time and fall time PIC16C76/77 (Master Mode) PIC16LC76/77 -- -- 45 ns -- -- 50 ns Data out rise time and fall time PIC16C76/77 -- -- 45 ns PIC16LC76/77 -- -- 50 ns Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 20-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 20-1 for load conditions TABLE 20-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter No. : Sym Characteristic Min Typ Max 125 TdtV2ckL 126 TckL2dtl Units Conditions SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) 15 -- -- ns Data hold after CK (DT hold time) 15 -- -- ns Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30390E-page 237 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20-13: A/D CONVERTER CHARACTERISTICS: PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) PIC16LC76/77-04 (Commercial, Industrial) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ Max Units Conditions -- -- 8-bits bit -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF A03 EIL A04 EDL Differential linearity error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A05 EFS Full scale error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A06 EOFF Offset error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A10 -- Integral linearity error Min VSS VAIN VREF Monotonicity -- guaranteed -- -- A20 VREF Reference voltage 3.0V -- VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 -- VREF + 0.3 V A30 ZAIN Recommended impedance of analog voltage source -- -- 10.0 k A40 IAD PIC16C76/77 -- 180 -- A PIC16LC76/77 -- 90 -- A 10 -- 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 13.1. -- -- 10 A During A/D Conversion cycle A50 A/D conversion current (VDD) IREF VREF input current (Note 2) Average current consumption when A/D is on. (Note 1) * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. DS30390E-page 238 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20-17: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 Tcy (TOSC/2) (1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 20-14: A/D CONVERSION REQUIREMENTS Param No. 130 Sym Characteristic TAD A/D clock period Min Typ Max Units Conditions PIC16C76/77 1.6 -- -- s TOSC based, VREF 3.0V PIC16LC76/77 2.0 -- -- s TOSC based, VREF full range PIC16C76/77 2.0 4.0 6.0 s A/D RC Mode A/D RC Mode PIC16LC76/77 3.0 6.0 9.0 s 131 TCNV Conversion time (not including S/H time) (Note 1) -- 9.5 -- TAD 132 TACQ Acquisition time Note 2 20 -- s 5* -- -- s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). -- TOSC/2 -- -- If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1.5 -- -- TAD 134 TGO Q4 to A/D clock start TSWC Switching from convert sample time 135 * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 13.1 for min conditions. 1997 Microchip Technology Inc. DS30390E-page 239 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 NOTES: DS30390E-page 240 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 21.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25C, while 'max' or 'min' represents (mean +3) and (mean -3) respectively where is standard deviation. FIGURE 21-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE) 35 30 IPD(nA) 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 FIGURE 21-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE) 10.000 85C 70C IPD(A) 1.000 25C 0.100 0C -40C 0.010 0.001 2.5 1997 Microchip Technology Inc. 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 DS30390E-page 241 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-3: TYPICAL IPD vs. VDD @ 25C (WDT ENABLED, RC MODE) FIGURE 21-5: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 22 pF, T = 25C 6.0 25 5.5 5.0 4.5 Fosc(MHz) IPD(A) 20 15 10 R = 5k 4.0 3.5 3.0 R = 10k 2.5 2.0 5 1.5 1.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 2.5 VDD(Volts) FIGURE 21-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE) 35 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 0C Cext = 100 pF, T = 25C 2.4 2.2 R = 3.3k 2.0 20 1.8 70C Fosc(MHz) IPD(A) 6.0 Shaded area is beyond recommended range. 25 15 85C 10 5 1.6 R = 5k 1.4 1.2 1.0 R = 10k 0.8 0.6 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.4 6.0 R = 100k 0.2 VDD(Volts) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 21-7: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 300 pF, T = 25C 1000 900 800 Fosc(kHz) Data based on matrix samples. See first page of this section for details. 5.5 FIGURE 21-6: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD -40C 30 R = 100k 0.5 6.0 R = 3.3k 700 600 R = 5k 500 400 R = 10k 300 200 R = 100k 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) DS30390E-page 242 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC MODE) FIGURE 21-10: TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE) 1400 1200 30 25 Device NOT in Brown-out Reset 800 20 600 400 200 0 2.5 IPD(A) IPD(A) 1000 Device in Brown-out Reset 15 10 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 5 6.0 0 2.5 The shaded region represents the built-in hysteresis of the brown-out reset circuitry. FIGURE 21-9: MAXIMUM IPD vs. VDD BROWN-OUT DETECT ENABLED (85C TO -40C, RC MODE) 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 FIGURE 21-11: MAXIMUM IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C TO -40C, RC MODE) 1600 1400 1200 45 40 Device NOT in Brown-out Reset 800 35 30 400 Device in Brown-out Reset 20 15 200 4.3 0 2.5 25 3.0 3.5 4.0 4.5 VDD(Volts) 10 5.0 5.5 6.0 The shaded region represents the built-in hysteresis of the brown-out reset circuitry. 1997 Microchip Technology Inc. 5 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 DS30390E-page 243 Data based on matrix samples. See first page of this section for details. 600 IPD(A) IPD(A) 1000 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V IDD(A) 1400 4.0V 1200 3.5V 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Frequency(MHz) 3.5 4.0 4.5 Shaded area is beyond recommended range FIGURE 21-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40C TO 85C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V IDD(A) Data based on matrix samples. See first page of this section for details. 1400 4.0V 1200 3.5V 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 Frequency(MHz) DS30390E-page 244 3.0 3.5 4.0 4.5 Shaded area is beyond recommended range 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(A) 3.5V 3.0V 800 2.5V 600 400 200 0 0 200 400 Shaded area is beyond recommended range 600 800 1000 1200 1400 1600 1800 Frequency(kHz) FIGURE 21-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40C TO 85C) 1600 6.0V 1400 5.0V 1200 4.5V 4.0V 1000 IDD(A) 3.5V 3.0V 800 2.5V 600 400 200 0 0 200 400 Shaded area is beyond recommended range 1997 Microchip Technology Inc. 600 800 1000 1200 1400 1600 1800 Frequency(kHz) DS30390E-page 245 Data based on matrix samples. See first page of this section for details. 5.5V PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V IDD(A) 3.0V 600 2.5V 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 21-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40C TO 85C) 1200 6.0V 5.5V 5.0V 4.5V 4.0V 800 3.5V IDD(A) Data based on matrix samples. See first page of this section for details. 1000 3.0V 600 2.5V 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) DS30390E-page 246 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-18: TYPICAL IDD vs. CAPACITANCE @ 500 kHz (RC MODE) FIGURE 21-19: TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD 600 4.0 3.5 3.0 gm(mA/V) 4.0V 400 IDD(A) Max -40C 5.0V 500 3.0V 300 200 2.5 Typ 25C 2.0 Min 85C 1.5 1.0 100 0.5 100 pF RC OSCILLATOR FREQUENCIES 100 300 pF 5k 4.12 MHz 1.4% 10k 2.35 MHz 1.4% 100k 268 kHz 1.1% 5.5 6.0 6.5 7.0 70 60 1.80 MHz 1.0% 1.27 MHz 1.0% 10k 688 kHz 1.2% 20 100k 77.2 kHz 1.0% 10 3.3k 707 kHz 1.4% 1.2% 10k 269 kHz 1.6% 100k 28.3 kHz 1.1% The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V. Typ 25C 50 5k 501 kHz Max -40C 80 3.3k 5k 5.0 90 gm(A/V) 100 pF 4.5 110 Rext Fosc @ 5V, 25C 22 pF 4.0 FIGURE 21-20: TRANSCONDUCTANCE(gm) OF LP OSCILLATOR vs. VDD Average Cext 3.5 VDD(Volts) Shaded area is beyond recommended range Capacitance(pF) TABLE 21-1: 0.0 3.0 300 pF 40 30 0 2.0 Min 85C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD(Volts) Shaded areas are beyond recommended range FIGURE 21-21: TRANSCONDUCTANCE(gm) OF XT OSCILLATOR vs. VDD 1000 900 Max -40C 800 gm(A/V) 700 600 Typ 25C 500 400 300 Min 85C 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD(Volts) Shaded areas are beyond recommended range 1997 Microchip Technology Inc. DS30390E-page 247 Data based on matrix samples. See first page of this section for details. 0 20 pF PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-22: TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25C) FIGURE 21-24: TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25C) 3.5 70 3.0 60 50 Startup Time(ms) Startup Time(Seconds) 2.5 2.0 32 kHz, 33 pF/33 pF 1.5 1.0 40 200 kHz, 68 pF/68 pF 30 200 kHz, 47 pF/47 pF 20 1 MHz, 15 pF/15 pF 10 0.5 4 MHz, 15 pF/15 pF 200 kHz, 15 pF/15 pF 0.0 2.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 6.0 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 VDD(Volts) FIGURE 21-23: TYPICAL XTAL STARTUP TIME vs. VDD (HS MODE, 25C) 7 Osc Type Startup Time(ms) 6 Data based on matrix samples. See first page of this section for details. TABLE 21-2: LP 20 MHz, 33 pF/33 pF 5 XT 4 8 MHz, 33 pF/33 pF 3 20 MHz, 15 pF/15 pF 8 MHz, 15 pF/15 pF 2 1 4.0 4.5 DS30390E-page 248 5.0 VDD(Volts) 5.5 HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATORS Crystal Freq Cap. Range C1 Cap. Range C2 33 pF 32 kHz 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF 6.0 Crystals Used 32 kHz Epson C-001R32.768K-A 20 PPM 200 kHz STD XTL 200.000KHz 20 PPM 1 MHz ECS ECS-10-13-1 50 PPM 4 MHz ECS ECS-40-20-1 50 PPM 8 MHz EPSON CA-301 8.000M-C 30 PPM 20 MHz EPSON CA-301 20.000M-C 30 PPM 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-25: TYPICAL IDD vs. FREQUENCY (LP MODE, 25C) FIGURE 21-27: TYPICAL IDD vs. FREQUENCY (XT MODE, 25C) 1800 1600 6.0V 1400 5.5V 120 100 5.0V 1200 4.5V 1000 4.0V 60 40 20 0 0 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V IDD(A) IDD(A) 80 3.5V 800 3.0V 600 2.5V 400 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 21-26: MAXIMUM IDD vs. FREQUENCY (LP MODE, 85C TO -40C) FIGURE 21-28: MAXIMUM IDD vs. FREQUENCY (XT MODE, -40C TO 85C) 1800 6.0V 1600 120 1400 100 1200 80 1000 4.0V 800 3.5V 40 20 0 0 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 5.5V 5.0V 4.5V 3.0V 600 2.5V 400 200 50 100 Frequency(kHz) 150 200 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) 1997 Microchip Technology Inc. DS30390E-page 249 Data based on matrix samples. See first page of this section for details. 60 IDD(A) IDD(A) 140 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21-29: TYPICAL IDD vs. FREQUENCY (HS MODE, 25C) 7.0 FIGURE 21-30: MAXIMUM IDD vs. FREQUENCY (HS MODE, -40C TO 85C) 7.0 6.0 6.0 5.0 IDD(mA) IDD(mA) 5.0 4.0 3.0 2.0 1.0 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4.0 3.0 2.0 1.0 4 6 8 10 12 Frequency(MHz) 14 16 18 20 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4 6 8 10 12 14 16 18 20 Data based on matrix samples. See first page of this section for details. Frequency(MHz) DS30390E-page 250 1997 Microchip Technology Inc. PIC16C7X 22.0 PACKAGING INFORMATION 22.1 28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil)(JW) N C E1 E eA eB Pin #1 Indicator Area D S1 S Base Plane Seating Plane L B1 A3 A2 A A1 e1 B D1 Package Group: Ceramic Side Brazed Dual In-Line (CER) Millimeters Inches Symbol A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 Min Max 0 3.937 1.016 2.921 1.930 0.406 1.219 0.228 35.204 32.893 7.620 7.366 2.413 7.366 7.594 3.302 28 1.143 0.533 10 5.030 1.524 3.506 2.388 0.508 1.321 0.305 35.916 33.147 8.128 7.620 2.667 7.874 8.179 4.064 28 1.397 0.737 1997 Microchip Technology Inc. Notes Typical Typical Reference Typical Reference Min Max 0 0.155 0.040 0.115 0.076 0.016 0.048 0.009 1.386 1.295 0.300 0.290 0.095 0.290 0.299 0.130 28 0.045 0.021 10 0.198 0.060 0.138 0.094 0.020 0.052 0.012 1.414 1.305 0.320 0.300 0.105 0.310 0.322 0.160 28 0.055 0.029 Notes DS30390E-page 251 PIC16C7X 22.2 40-Lead Ceramic CERDIP Dual In-line with Window (600 mil) (JW) N E1 E C Pin No. 1 Indicator Area eA eB D S S1 Base Plane Seating Plane L B1 A1 A3 A A2 e1 B D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Symbol Min Max 0 A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 4.318 0.381 3.810 3.810 0.355 1.270 0.203 51.435 48.260 15.240 12.954 2.540 14.986 15.240 3.175 40 1.016 0.381 DS30390E-page 252 Inches Notes Min Max 10 0 10 5.715 1.778 4.699 4.445 0.585 1.651 0.381 52.705 48.260 15.875 15.240 2.540 16.002 18.034 3.810 40 2.286 1.778 0.170 0.015 0.150 0.150 0.014 0.050 0.008 2.025 1.900 0.600 0.510 0.100 0.590 0.600 0.125 40 0.040 0.015 0.225 0.070 0.185 0.175 0.023 0.065 0.015 2.075 1.900 0.625 0.600 0.100 0.630 0.710 0.150 40 0.090 0.070 Typical Typical Reference Reference Typical Notes Typical Typical Reference Reference Typical 1997 Microchip Technology Inc. PIC16C7X 22.3 28-Lead Plastic Dual In-line (300 mil) (SP) N E1 E C eA eB Pin No. 1 Indicator Area B2 D B1 S Base Plane Seating Plane L Detail A B3 A1 A2 A e1 B Detail A D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max 0 A A1 A2 B B1 B2 B3 C D D1 E E1 e1 eA eB L N S 3.632 0.381 3.175 0.406 1.016 0.762 0.203 0.203 34.163 33.020 7.874 7.112 2.540 7.874 8.128 3.175 28 0.584 1997 Microchip Technology Inc. Inches Notes Min Max 10 0 10 4.572 - 3.556 0.559 1.651 1.016 0.508 0.331 35.179 33.020 8.382 7.493 2.540 7.874 9.652 3.683 1.220 0.143 0.015 0.125 0.016 0.040 0.030 0.008 0.008 1.385 1.300 0.310 0.280 0.100 0.310 0.320 0.125 28 0.023 0.180 - 0.140 0.022 0.065 0.040 0.020 0.013 1.395 1.300 0.330 0.295 0.100 0.310 0.380 0.145 0.048 Typical 4 places 4 places Typical Reference Typical Reference Notes Typical 4 places 4 places Typical Reference Typical Reference DS30390E-page 253 PIC16C7X 22.4 40-Lead Plastic Dual In-line (600 mil) (P) N E1 E C eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max 0 A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 - 0.381 3.175 0.355 1.270 0.203 51.181 48.260 15.240 13.462 2.489 15.240 15.240 2.921 40 1.270 0.508 DS30390E-page 254 Inches Notes Min Max 10 0 10 5.080 - 4.064 0.559 1.778 0.381 52.197 48.260 15.875 13.970 2.591 15.240 17.272 3.683 40 - - - 0.015 0.125 0.014 0.050 0.008 2.015 1.900 0.600 0.530 0.098 0.600 0.600 0.115 40 0.050 0.020 0.200 - 0.160 0.022 0.070 0.015 2.055 1.900 0.625 0.550 0.102 0.600 0.680 0.145 40 - - Typical Typical Reference Typical Reference Notes Typical Typical Reference Typical Reference 1997 Microchip Technology Inc. PIC16C7X 22.5 28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO) e B h x 45 N Index Area E H C Chamfer h x 45 L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Symbol Min Max Inches Notes Min Max 0 8 0 8 A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 17.703 7.416 1.270 10.007 0.381 0.406 28 - 2.642 0.300 0.483 0.318 18.085 7.595 1.270 10.643 0.762 1.143 28 0.102 0.093 0.004 0.014 0.009 0.697 0.292 0.050 0.394 0.015 0.016 28 - 0.104 0.012 0.019 0.013 0.712 0.299 0.050 0.419 0.030 0.045 28 0.004 1997 Microchip Technology Inc. Typical Notes Typical DS30390E-page 255 PIC16C7X 22.6 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS) N Index area E H C L 1 2 3 B e A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Symbol Min Max Inches Notes Min Max 0 8 0 8 A A1 B C D E e H L N CP 1.730 0.050 0.250 0.130 10.070 5.200 0.650 7.650 0.550 28 - 1.990 0.210 0.380 0.220 10.330 5.380 0.650 7.900 0.950 28 0.102 0.068 0.002 0.010 0.005 0.396 0.205 0.026 0.301 0.022 28 - 0.078 0.008 0.015 0.009 0.407 0.212 0.026 0.311 0.037 28 0.004 DS30390E-page 256 Reference Notes Reference 1997 Microchip Technology Inc. PIC16C7X 22.7 44-Lead Plastic Leaded Chip Carrier (Square)(PLCC) D -A- D1 -D- 3 -F- 0.812/0.661 N Pics .032/.026 1.27 .050 2 Sides 0.177 .007 S B D-E S -HA A1 3 D3/E3 D2 0.38 .015 3 -G- 8 F-G S 0.177 .007 S B A S 2 Sides 9 0.101 Seating .004 Plane D -C- 4 E2 E1 E 0.38 .015 F-G S 4 -B- 3 -E- 0.177 .007 S A F-G S 10 0.254 .010 Max 2 0.254 .010 Max 11 -H- 11 0.508 .020 0.508 .020 -H- 2 0.812/0.661 3 .032/.026 1.524 .060 Min 6 6 -C1.651 .065 1.651 .065 R 1.14/0.64 .045/.025 R 1.14/0.64 .045/.025 5 0.533/0.331 .021/.013 0.64 Min .025 0.177 , D-E S .007 M A F-G S Package Group: Plastic Leaded Chip Carrier (PLCC) Millimeters Symbol Min Max A 4.191 A1 D D1 D2 D3 E E1 E2 E3 N CP LT 2.413 17.399 16.510 15.494 12.700 17.399 16.510 15.494 12.700 44 - 0.203 1997 Microchip Technology Inc. Inches Notes Min Max 4.572 0.165 0.180 2.921 17.653 16.663 16.002 12.700 17.653 16.663 16.002 12.700 44 0.102 0.381 0.095 0.685 0.650 0.610 0.500 0.685 0.650 0.610 0.500 44 - 0.008 0.115 0.695 0.656 0.630 0.500 0.695 0.656 0.630 0.500 44 0.004 0.015 Reference Reference Notes Reference Reference DS30390E-page 257 PIC16C7X 22.8 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) (PQ) 4 D D1 5 0.20 M C A-B S D S 0.20 M H A-B S D S 7 0.20 min. 0.05 mm/mm A-B D3 0.13 R min. Index area 6 9 PARTING LINE 0.13/0.30 R b L C E3 E1 E 1.60 Ref. 0.20 M C A-B S D S 4 TYP 4x 10 e 0.20 M H A-B S B D S 5 7 0.05 mm/mm D A2 A Base Plane Seating Plane A1 Package Group: Plastic MQFP Millimeters Symbol Min Max Inches Notes Min Max 0 7 0 7 A A1 A2 b C D D1 D3 E E1 E3 e L N CP 2.000 0.050 1.950 0.300 0.150 12.950 9.900 8.000 12.950 9.900 8.000 0.800 0.730 44 0.102 2.350 0.250 2.100 0.450 0.180 13.450 10.100 8.000 13.450 10.100 8.000 0.800 1.030 44 - 0.078 0.002 0.768 0.011 0.006 0.510 0.390 0.315 0.510 0.390 0.315 0.031 0.028 44 0.004 0.093 0.010 0.083 0.018 0.007 0.530 0.398 0.315 0.530 0.398 0.315 0.032 0.041 44 - DS30390E-page 258 Typical Reference Reference Notes Typical Reference Reference 1997 Microchip Technology Inc. PIC16C7X 22.9 44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form) (TQ) D D1 1.0o (0.039o) Ref. Pin#1 2 11/13(4x) Pin#1 2 E 0 Min E1 11/13(4x) Detail B e 3.0o (0.118o) Ref. Option 1 (TOP side) A2 A L Detail A R 0.08/0.20 Option 2 (TOP side) A1 Detail B R1 0.08 Min Base Metal Lead Finish b L c 1.00 Ref. Gage Plane 0.250 c1 L1 1.00 Ref b1 Detail A S 0.20 Min Detail B Package Group: Plastic TQFP Millimeters Inches Symbol Min Max A A1 A2 D D1 E E1 L e b b1 c c1 N 1.00 0.05 0.95 11.75 9.90 11.75 9.90 0.45 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.75 Notes Min Max 0.039 0.002 0.037 0.463 0.390 0.463 0.390 0.018 0.047 0.006 0.041 0.482 0.398 0.482 0.398 0.030 0.30 0.30 0.09 0.09 44 0.45 0.40 0.20 0.16 44 0.012 0.012 0.004 0.004 44 0.018 0.016 0.008 0.006 44 0 7 0 7 0.80 BSC Notes 0.031 BSC Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010") per side. D1 and E1 dimensions including mold mismatch. 2: Dimension "b" does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m (0.003")max. 3: This outline conforms to JEDEC MS-026. 1997 Microchip Technology Inc. DS30390E-page 259 PIC16C7X 22.10 Package Marking Information 28-Lead SSOP Example XXXXXXXXXXXX XXXXXXXXXXXX PIC16C72 20I/SS025 AABBCAE 9517SBP 28-Lead PDIP (Skinny DIP) Example MMMMMMMMMMMM XXXXXXXXXXXXXXX AABBCDE PIC16C73-10/SP AABBCDE 28-Lead Side Brazed Skinny Windowed Example XXXXXXXXXXX XXXXXXXXXXX AABBCDE MMMMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXXXX AABBCDE MM...M XX...X AA BB C D1 E Note: 9517CAT Example 28-Lead SOIC Legend: PIC16C73/JW PIC16C73-10/SO 945/CAA Microchip part number information Customer specific information* Year code (last 2 digits of calender year) Week code (week of January 1 is week '01') Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. Mask revision number for microcontroller Assembly code of the plant or country of origin in which part was assembled. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30390E-page 260 1997 Microchip Technology Inc. PIC16C7X Package Marking Information (Cont'd) 40-Lead PDIP Example MMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXX AABBCDE 40-Lead CERDIP Windowed PIC16C74-04/P 9512CAA Example MMMMMMMMM XXXXXXXXXXX XXXXXXXXXXX AABBCDE 44-Lead PLCC 44-Lead MQFP PIC16C74 -10/L AABBCDE Example PIC16C74 -10/PQ MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE AABBCDE MM...M XX...X AA BB C D1 E Note: AABBCDE Example MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE Legend: PIC16C74/JW Microchip part number information Customer specific information* Year code (last 2 digits of calender year) Week code (week of January 1 is week '01') Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. Mask revision number for microcontroller Assembly code of the plant or country of origin in which part was assembled. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1997 Microchip Technology Inc. DS30390E-page 261 PIC16C7X Package Marking Information (Cont'd) 44-Lead TQFP Example MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE Legend: PIC16C74A -10/TQ AABBCDE MM...M XX...X AA BB C D1 E Note: Microchip part number information Customer specific information* Year code (last 2 digits of calender year) Week code (week of January 1 is week '01') Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. Mask revision number for microcontroller Assembly code of the plant or country of origin in which part was assembled. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30390E-page 262 1997 Microchip Technology Inc. PIC16C7X APPENDIX A: APPENDIX B: COMPATIBILITY The following are the list of modifications over the PIC16C5X microcontroller family: To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. Bits PA2, PA1, PA0 are removed from STATUS register. Data memory paging is redefined slightly. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change feature. T0CKI pin is also a port pin (RA4) now. FSR is made a full eight bit register. "In-circuit serial programming" is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). PCON status register is added with a Power-on Reset status bit (POR). Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. Brown-out protection circuitry has been added. Controlled by configuration word bit BODEN. Brown-out reset ensures the device is placed in a reset condition if VDD dips below a fixed setpoint. 1997 Microchip Technology Inc. 2. 3. 4. 5. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h. DS30390E-page 263 PIC16C7X APPENDIX C: WHAT'S NEW APPENDIX D: WHAT'S CHANGED Added the following devices: Minor changes, spelling and grammatical changes. * PIC16C76 * PIC16C77 Added the following note to the USART section. This note applies to all devices except the PIC16C76 and PIC16C77. Removed the PIC16C710, PIC16C71, PIC16C711 from this datasheet. Added PIC16C76 and PIC16C77 devices. The PIC16C76/77 devices have 368 bytes of data memory distributed in 4 banks and 8K of program memory in 4 pages. These two devices have an enhanced SPI that supports both clock phase and polarity. The USART has been enhanced. When upgrading to the PIC16C76/77 please note that the upper 16 bytes of data memory in banks 1,2, and 3 are mapped into bank 0. This may require relocation of data memory usage in the user application code. For the PIC16C73/73A/74/74A the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information or use the PIC16C76/77. Divided SPI section into SPI for the PIC16C76/77 and SPI for all other devices. Added Q-cycle definitions to the Instruction Set Summary section. DS30390E-page 264 1997 Microchip Technology Inc. PIC16C7X APPENDIX E: PIC16/17 MICROCONTROLLERS E.1 PIC12CXXX Family of Devices PIC12C508 Maximum Frequency of Operation (MHz) Clock Memory Peripherals Features 4 PIC12C509 4 PIC12C671 4 PIC12C672 4 EPROM Program Memory 512 x 12 1024 x 12 1024 x 14 2048 x 14 Data Memory (bytes) 25 41 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 A/D Converter (8-bit) Channels -- -- 4 4 Wake-up from SLEEP on pin change Yes Yes Yes Yes I/O Pins 5 5 5 5 Input Pins 1 1 1 1 Internal Pull-ups Yes Yes Yes Yes Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Number of Instructions 33 33 35 35 Packages 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC All PIC12C5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12C5XX devices use serial programming with data pin GP1 and clock pin GP0. E.2 PIC14C000 Family of Devices PIC14C000 Clock Memory Peripherals Features Maximum Frequency of Operation (MHz) 20 EPROM Program Memory (x14 words) 4K Data Memory (bytes) 192 Timer Module(s) TMR0 ADTMR Serial Port(s) (SPI/I2C, USART) I2C with SMBus Support Slope A/D Converter Channels 8 External; 6 Internal Interrupt Sources 11 I/O Pins 22 Voltage Range (Volts) 2.7-6.0 In-Circuit Serial Programming Yes Additional On-chip Features Internal 4MHz Oscillator, Bandgap Reference,Temperature Sensor, Calibration Factors, Low Voltage Detector, SLEEP, HIBERNATE, Comparators with Programmable References (2) Packages 28-pin DIP (.300 mil), SOIC, SSOP 1997 Microchip Technology Inc. DS30390E-page 265 PIC16C7X E.3 PIC16C15X Family of Devices PIC16C154 Clock Memory PIC16C156 PIC16CR156 PIC16C158 PIC16CR158 20 20 20 20 20 20 EPROM Program Memory (x12 words) 512 -- 1K -- 2K -- ROM Program Memory (x12 words) -- 512 -- 1K -- 2K 73 RAM Data Memory (bytes) 25 25 25 25 73 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 12 12 12 12 Voltage Range (Volts) 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 Number of Instructions 33 33 33 33 33 33 Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP Peripherals Timer Module(s) Features PIC16CR154 Maximum Frequency of Operation (MHz) All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. E.4 PIC16C5X Family of Devices PIC16C52 Clock Memory PIC16C54A 20 20 20 20 EPROM Program Memory (x12 words) 384 512 512 -- 512 1K ROM Program Memory (x12 words) -- -- -- 512 -- -- 25 25 25 25 25 24 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 12 12 12 12 20 12 Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.25 Number of Instructions 33 33 33 33 33 33 Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 20-pin SSOP PIC16C57 PIC16CR57B PIC16C58A PIC16CR58A Maximum Frequency of Operation (MHz) 20 20 20 20 EPROM Program Memory (x12 words) 2K -- 2K -- ROM Program Memory (x12 words) -- 2K -- 2K 73 RAM Data Memory (bytes) 72 72 73 TMR0 TMR0 TMR0 TMR0 I/O Pins 20 20 12 12 Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.5-6.25 Number of Instructions 33 33 33 33 Packages 28-pin DIP, SOIC, SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 18-pin DIP, SOIC; 20-pin SSOP 20-pin SSOP Peripherals Timer Module(s) Features PIC16C56 20 I/O Pins Memory PIC16C55 4 RAM Data Memory (bytes) Clock PIC16CR54A Maximum Frequency of Operation (MHz) Peripherals Timer Module(s) Features PIC16C54 All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and high I/O current capability. DS30390E-page 266 1997 Microchip Technology Inc. PIC16C7X E.5 PIC16C55X Family of Devices PIC16C556(1) PIC16C554 Clock Memory 20 20 20 EPROM Program Memory (x14 words) 512 1K 2K Data Memory (bytes) 80 80 128 Timer Module(s) TMR0 TMR0 TMR0 -- -- -- -- -- -- Peripherals Comparators(s) Internal Reference Voltage Features PIC16C558 Maximum Frequency of Operation (MHz) Interrupt Sources 3 3 3 I/O Pins 13 13 13 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 Brown-out Reset -- -- -- Packages 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C5XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices. E.6 PIC16C62X and PIC16C64X Family of Devices PIC16C620 Clock Memory PIC16C622 PIC16C642 PIC16C662 Maximum Frequency of Operation (MHz) 20 20 20 20 20 EPROM Program Memory (x14 words) 512 1K 2K 4K 4K Data Memory (bytes) 80 80 128 176 176 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 2 Peripherals Comparators(s) Features PIC16C621 2 2 2 2 Internal Reference Voltage Yes Yes Yes Yes Yes Interrupt Sources 4 4 4 4 5 I/O Pins 13 13 13 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 3.0-6.0 3.0-6.0 Brown-out Reset Yes Yes Yes Yes Yes Packages 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin PDIP, SOIC, Windowed CDIP 40-pin PDIP, Windowed CDIP; 44-pin PLCC, MQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C62X and PIC16C64X Family devices use serial programming with clock pin RB6 and data pin RB7. 1997 Microchip Technology Inc. DS30390E-page 267 PIC16C7X E.7 PIC16C6X Family of Devices PIC16C61 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63 Maximum Frequency of Operation (MHz) 20 20 20 20 20 EPROM Program Memory (x14 words) 1K 2K -- 4K -- ROM Program Memory (x14 words) -- -- 2K -- 4K Data Memory (bytes) 36 128 128 192 192 Timer Module(s) TMR0 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/ Peripherals PWM Module(s) -- 1 1 2 2 Serial Port(s) (SPI/I2C, USART) -- SPI/I2C SPI/I2C SPI/I2C, USART SPI/I2C USART Parallel Slave Port -- -- -- -- -- Clock Memory Features Interrupt Sources 3 7 7 10 10 I/O Pins 13 22 22 22 22 Voltage Range (Volts) 3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Yes Brown-out Reset -- Yes Yes Yes Yes Packages 18-pin DIP, SO 28-pin SDIP, SOIC, SSOP 28-pin SDIP, SOIC, SSOP 28-pin SDIP, 28-pin SDIP, SOIC SOIC PIC16C64A Clock Memory PIC16C65A PIC16CR65 PIC16C66 PIC16C67 Maximum Frequency of Operation (MHz) 20 20 20 20 20 20 EPROM Program Memory (x14 words) 2K -- 4K -- 8K 8K ROM Program Memory (x14 words) -- 2K -- 4K -- -- Data Memory (bytes) 128 128 192 192 368 368 Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 1 1 2 2 2 2 Serial Port(s) (SPI/I2C, USART) SPI/I2C SPI/I2C SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART Parallel Slave Port Yes Yes Yes Yes -- Yes Interrupt Sources 8 8 11 11 10 11 I/O Pins 33 33 33 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Brown-out Reset Yes Yes Yes Yes Yes Yes Packages 40-pin DIP; 40-pin DIP; 40-pin DIP; 40-pin DIP; 44-pin PLCC, 44-pin PLCC, 44-pin PLCC, 44-pin MQFP, TQFP MQFP, TQFP MQFP, TQFP PLCC, MQFP, TQFP Capture/Compare/PWM ModPeripherals ule(s) Features PIC16CR64 28-pin SDIP, 40-pin DIP; SOIC 44-pin PLCC, MQFP, TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7. DS30390E-page 268 1997 Microchip Technology Inc. PIC16C7X E.8 PIC16C8X Family of Devices PIC16F83 Clock Memory Peripherals Features PIC16CR83 PIC16F84 PIC16CR84 Maximum Frequency of Operation (MHz) 10 10 10 10 Flash Program Memory 512 -- 1K -- EEPROM Program Memory -- -- -- -- ROM Program Memory -- 512 -- 1K Data Memory (bytes) 36 36 68 68 Data EEPROM (bytes) 64 64 64 64 Timer Module(s) TMR0 TMR0 TMR0 TMR0 Interrupt Sources 4 4 4 4 I/O Pins 13 13 13 13 Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0 Packages 18-pin DIP, SOIC 18-pin DIP, SOIC 18-pin DIP, SOIC 18-pin DIP, SOIC All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C8X Family devices use serial programming with clock pin RB6 and data pin RB7. E.9 PIC16C9XX Family Of Devices PIC16C923 Clock Memory 8 8 EPROM Program Memory 4K 4K Data Memory (bytes) 176 176 Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/PWM Module(s) 1 1 SPI/I2C SPI/I2C Parallel Slave Port -- -- A/D Converter (8-bit) Channels -- 5 LCD Module 4 Com, 32 Seg 4 Com, 32 Seg Interrupt Sources 8 9 I/O Pins 25 25 Input Pins 27 27 Voltage Range (Volts) 3.0-6.0 3.0-6.0 In-Circuit Serial Programming Yes Yes Serial Port(s) Peripherals (SPI/I2C, USART) Features PIC16C924 Maximum Frequency of Operation (MHz) Brown-out Reset -- -- Packages 64-pin SDIP(1), TQFP; 68-pin PLCC, Die 64-pin SDIP(1), TQFP; 68-pin PLCC, Die All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7. 1997 Microchip Technology Inc. DS30390E-page 269 PIC16C7X E.10 PIC17CXXX Family of Devices PIC17C42A Clock Memory Clock Memory PIC17CR43 PIC17C44 33 33 33 33 EPROM Program Memory (words) 2K -- 4K -- 8K ROM Program Memory (words) -- 2K -- 4K -- RAM Data Memory (bytes) 232 232 454 454 454 Timer Module(s) TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 Captures/PWM Module(s) 2 2 2 2 2 Serial Port(s) (USART) Yes Yes Yes Yes Yes Hardware Multiply Yes Yes Yes Yes Yes External Interrupts Yes Yes Yes Yes Yes Interrupt Sources 11 11 11 11 11 I/O Pins 33 33 33 33 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 Number of Instructions 58 58 58 58 58 Packages 40-pin DIP; 44-pin PLCC, MQFP, TQFP 40-pin DIP; 44-pin PLCC, MQFP, TQFP 40-pin DIP; 44-pin PLCC, MQFP, TQFP 40-pin DIP; 44-pin PLCC, MQFP, TQFP 40-pin DIP; 44-pin PLCC, MQFP, TQFP PIC17C752 PIC17C756 Maximum Frequency of Operation (MHz) 33 33 EPROM Program Memory (words) 8K 16K ROM Program Memory (words) -- -- RAM Data Memory (bytes) 454 902 Timer Module(s) TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 Peripherals Features PIC17C43 33 Peripherals Features PIC17CR42 Maximum Frequency of Operation (MHz) Captures/PWM Module(s) 4/3 4/3 Serial Port(s) (USART) 2 2 Hardware Multiply Yes Yes External Interrupts Yes Yes Interrupt Sources 18 18 I/O Pins 50 50 Voltage Range (Volts) 3.0-6.0 3.0-6.0 Number of Instructions 58 58 Packages 64-pin DIP; 68-pin LCC, 68-pin TQFP 64-pin DIP; 68-pin LCC, 68-pin TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. DS30390E-page 270 1997 Microchip Technology Inc. PIC16C7X PIN COMPATIBILITY Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55. Pin compatibility does not mean that the devices offer the same features. As an example, the PIC16C54 is pin compatible with the PIC16C71, but does not have an A/D converter, weak pull-ups on PORTB, or interrupts. TABLE E-1: PIN COMPATIBLE DEVICES Pin Compatible Devices Package PIC12C508, PIC12C509, PIC12C671, PIC12C672 8-pin PIC16C154, PIC16CR154, PIC16C156, PIC16CR156, PIC16C158, PIC16CR158, PIC16C52, PIC16C54, PIC16C54A, PIC16CR54A, PIC16C56, PIC16C58A, PIC16CR58A, PIC16C61, PIC16C554, PIC16C556, PIC16C558 PIC16C620, PIC16C621, PIC16C622 PIC16C641, PIC16C642, PIC16C661, PIC16C662 PIC16C710, PIC16C71, PIC16C711, PIC16C715 PIC16F83, PIC16CR83, PIC16F84A, PIC16CR84 18-pin, 20-pin PIC16C55, PIC16C57, PIC16CR57B 28-pin PIC16CR62, PIC16C62A, PIC16C63, PIC16CR63, PIC16C66, PIC16C72, PIC16C73A, PIC16C76 28-pin PIC16CR64, PIC16C64A, PIC16C65A, PIC16CR65, PIC16C67, PIC16C74A, PIC16C77 40-pin PIC17CR42, PIC17C42A, PIC17C43, PIC17CR43, PIC17C44 40-pin PIC16C923, PIC16C924 64/68-pin PIC17C756, PIC17C752 64/68-pin 1997 Microchip Technology Inc. DS30390E-page 271 PIC16C7X NOTES: DS30390E-page 272 1997 Microchip Technology Inc. PIC16C7X INDEX A A/D Accuracy/Error ......................................................... 124 ADCON0 Register .................................................... 117 ADCON1 Register .................................................... 118 ADIF bit .................................................................... 119 Analog Input Model Block Diagram .......................... 120 Analog-to-Digital Converter ...................................... 117 Block Diagram .......................................................... 119 Configuring Analog Port Pins ................................... 121 Configuring the Interrupt .......................................... 119 Configuring the Module ............................................ 119 Connection Considerations ...................................... 125 Conversion Clock ..................................................... 121 Conversion Time ...................................................... 123 Conversions ............................................................. 122 Converter Characteristics ................ 181, 199, 217, 238 Delays ...................................................................... 120 Effects of a Reset ..................................................... 124 Equations ................................................................. 120 Faster Conversion - Lower Resolution Tradeoff ...... 123 Flowchart of A/D Operation ...................................... 126 GO/DONE bit ........................................................... 119 Internal Sampling Switch (Rss) Impedance ............. 120 Operation During Sleep ........................................... 124 Sampling Requirements ........................................... 120 Sampling Time ......................................................... 120 Source Impedance ................................................... 120 Time Delays ............................................................. 120 Transfer Function ..................................................... 125 Using the CCP Trigger ............................................. 125 Absolute Maximum Ratings ..................... 167, 183, 201, 219 ACK ........................................................................ 90, 94, 95 ADIE bit .............................................................................. 33 ADIF bit .............................................................................. 35 ADRES Register .................................... 23, 25, 27, 117, 119 ALU ...................................................................................... 9 Application Notes AN546 (Using the Analog-to-Digital Converter) ....... 117 AN552 (Implementing Wake-up on Key Strokes Using PIC16CXXX) .............................................................. 45 AN556 (Table Reading Using PIC16CXX .................. 40 AN578 (Use of the SSP Module in the I2C Multi-Master Environment) .............................................................. 77 AN594 (Using the CCP Modules) .............................. 71 AN607, Power-up Trouble Shooting ........................ 134 Architecture Harvard ........................................................................ 9 Overview ...................................................................... 9 von Neumann ............................................................... 9 Assembler MPASM Assembler .................................................. 164 B Baud Rate Error ............................................................... 101 Baud Rate Formula .......................................................... 101 Baud Rates Asynchronous Mode ................................................ 102 Synchronous Mode .................................................. 102 BF .......................................................................... 78, 83, 94 Block Diagrams A/D ........................................................................... 119 Analog Input Model .................................................. 120 Capture ...................................................................... 72 1997 Microchip Technology Inc. Compare .....................................................................73 I2C Mode ....................................................................93 On-Chip Reset Circuit ...............................................133 PIC16C72 ...................................................................10 PIC16C73 ...................................................................11 PIC16C73A .................................................................11 PIC16C74 ...................................................................12 PIC16C74A .................................................................12 PIC16C76 ...................................................................11 PIC16C77 ...................................................................12 PORTC .......................................................................48 PORTD (In I/O Port Mode) .........................................50 PORTD and PORTE as a Parallel Slave Port ............54 PORTE (In I/O Port Mode) .........................................51 PWM ...........................................................................74 RA3:RA0 and RA5 Port Pins ......................................43 RA4/T0CKI Pin ...........................................................43 RB3:RB0 Port Pins .....................................................45 RB7:RB4 Port Pins .....................................................46 SPI Master/Slave Connection .....................................81 SSP in I2C Mode ........................................................93 SSP in SPI Mode ..................................................80, 85 Timer0 ........................................................................59 Timer0/WDT Prescaler ...............................................62 Timer1 ........................................................................66 Timer2 ........................................................................69 USART Receive .......................................................108 USART Transmit ......................................................106 Watchdog Timer .......................................................144 BOR bit .......................................................................39, 135 BRGH bit ..........................................................................101 Buffer Full Status bit, BF ...............................................78, 83 C C bit ....................................................................................30 C Compiler ........................................................................165 Capture/Compare/PWM Capture Block Diagram ....................................................72 CCP1CON Register ...........................................72 CCP1IF ...............................................................72 CCPR1 ...............................................................72 CCPR1H:CCPR1L .............................................72 Mode ..................................................................72 Prescaler ............................................................73 CCP Timer Resources ................................................71 Compare Block Diagram ....................................................73 Mode ..................................................................73 Software Interrupt Mode .....................................73 Special Event Trigger .........................................73 Special Trigger Output of CCP1 .........................73 Special Trigger Output of CCP2 .........................73 Interaction of Two CCP Modules ................................71 Section ........................................................................71 Special Event Trigger and A/D Conversions ..............73 Capture/Compare/PWM (CCP) PWM Block Diagram ..................................................74 PWM Mode .................................................................74 PWM, Example Frequencies/Resolutions ..................75 Carry bit ................................................................................9 CCP1CON ..........................................................................29 CCP1IE bit ..........................................................................33 CCP1IF bit ....................................................................35, 36 CCP2CON ..........................................................................29 CCP2IE bit ..........................................................................37 DS30390E-page 273 PIC16C7X CCP2IF bit .......................................................................... 38 CCPR1H Register ............................................ 25, 27, 29, 71 CCPR1L Register ......................................................... 29, 71 CCPR2H Register ............................................ 25, 27, 29, 71 CCPR2L Register ............................................. 25, 27, 29, 71 CCPxM0 bit ........................................................................ 72 CCPxM1 bit ........................................................................ 72 CCPxM2 bit ........................................................................ 72 CCPxM3 bit ........................................................................ 72 CCPxX bit ........................................................................... 72 CCPxY bit ........................................................................... 72 CKE .................................................................................... 83 CKP .............................................................................. 79, 84 Clock Polarity Select bit, CKP ...................................... 79, 84 Clock Polarity, SPI Mode ................................................... 81 Clocking Scheme ............................................................... 17 Code Examples Call of a Subroutine in Page 1 from Page 0 ............... 41 Changing Between Capture Prescalers ..................... 73 Changing Prescaler (Timer0 to WDT) ........................ 63 Changing Prescaler (WDT to Timer0) ........................ 63 I/O Programming ........................................................ 53 Indirect Addressing .................................................... 41 Initializing PORTA ...................................................... 43 Initializing PORTB ...................................................... 45 Initializing PORTC ...................................................... 48 Loading the SSPBUF Register ............................ 80, 85 Code Protection ....................................................... 129, 146 Computed GOTO ............................................................... 40 Configuration Bits ............................................................. 129 Configuration Word .......................................................... 129 Connecting Two Microcontrollers ....................................... 81 CREN bit .......................................................................... 100 CS pin ................................................................................ 54 D D/A ............................................................................... 78, 83 Data/Address bit, D/A ................................................... 78, 83 DC bit ................................................................................. 30 DC Characteristics PIC16C72 ................................................................ 168 PIC16C73 ................................................................ 184 PIC16C73A .............................................................. 202 PIC16C74 ................................................................ 184 PIC16C74A .............................................................. 202 PIC16C76 ................................................................ 221 PIC16C77 ................................................................ 221 Development Support .................................................. 5, 163 Development Tools .......................................................... 163 Digit Carry bit ....................................................................... 9 Direct Addressing ............................................................... 41 E Electrical Characteristics PIC16C72 ................................................................ 167 PIC16C73 ................................................................ 183 PIC16C73A .............................................................. 201 PIC16C74 ................................................................ 183 PIC16C74A .............................................................. 201 PIC16C76 ................................................................ 219 PIC16C77 ................................................................ 219 External Brown-out Protection Circuit .............................. 140 External Power-on Reset Circuit ...................................... 140 DS30390E-page 274 F Family of Devices PIC12CXXX ............................................................. 265 PIC14C000 .............................................................. 265 PIC16C15X .............................................................. 266 PIC16C55X .............................................................. 267 PIC16C5X ................................................................ 266 PIC16C62X and PIC16C64X ................................... 267 PIC16C6X ................................................................ 268 PIC16C7XX ................................................................. 6 PIC16C8X ................................................................ 269 PIC16C9XX ............................................................. 269 PIC17CXX ............................................................... 270 FERR bit .......................................................................... 100 FSR Register ........................... 23, 24, 25, 26, 27, 28, 29, 41 Fuzzy Logic Dev. System (fuzzyTECH-MP) ......... 163, 165 G General Description ............................................................. 5 GIE bit .............................................................................. 141 I I/O Ports PORTA ...................................................................... 43 PORTB ...................................................................... 45 PORTC ...................................................................... 48 PORTD ................................................................ 50, 54 PORTE ...................................................................... 51 Section ....................................................................... 43 I/O Programming Considerations ...................................... 53 I2C Addressing ................................................................. 94 Addressing I2C Devices ............................................. 90 Arbitration .................................................................. 92 Block Diagram ........................................................... 93 Clock Synchronization ............................................... 92 Combined Format ...................................................... 91 I2C Operation ............................................................. 93 I2C Overview ............................................................. 89 Initiating and Terminating Data Transfer ................... 89 Master Mode .............................................................. 97 Master-Receiver Sequence ....................................... 91 Master-Transmitter Sequence ................................... 91 Mode .......................................................................... 93 Mode Selection .......................................................... 93 Multi-master ............................................................... 92 Multi-Master Mode ..................................................... 97 Reception .................................................................. 95 Reception Timing Diagram ........................................ 95 SCL and SDA pins ..................................................... 94 Slave Mode ................................................................ 94 START ....................................................................... 89 STOP ................................................................... 89, 90 Transfer Acknowledge ............................................... 90 Transmission ............................................................. 96 IDLE_MODE ...................................................................... 98 In-Circuit Serial Programming .................................. 129, 146 INDF .................................................................................. 29 INDF Register ...................................... 24, 25, 26, 27, 28, 41 Indirect Addressing ............................................................ 41 Initialization Condition for all Register .............................. 136 Instruction Cycle ................................................................ 17 Instruction Flow/Pipelining ................................................. 17 Instruction Format ............................................................ 147 1997 Microchip Technology Inc. PIC16C7X Instruction Set ADDLW .................................................................... 149 ADDWF .................................................................... 149 ANDLW .................................................................... 149 ANDWF .................................................................... 149 BCF .......................................................................... 150 BSF .......................................................................... 150 BTFSC ..................................................................... 150 BTFSS ..................................................................... 151 CALL ........................................................................ 151 CLRF ........................................................................ 152 CLRW ...................................................................... 152 CLRWDT .................................................................. 152 COMF ...................................................................... 153 DECF ....................................................................... 153 DECFSZ ................................................................... 153 GOTO ...................................................................... 154 INCF ......................................................................... 154 INCFSZ .................................................................... 155 IORLW ..................................................................... 155 IORWF ..................................................................... 156 MOVF ....................................................................... 156 MOVLW ................................................................... 156 MOVWF ................................................................... 156 NOP ......................................................................... 157 OPTION ................................................................... 157 RETFIE .................................................................... 157 RETLW .................................................................... 158 RETURN .................................................................. 158 RLF .......................................................................... 159 RRF .......................................................................... 159 SLEEP ..................................................................... 160 SUBLW .................................................................... 160 SUBWF .................................................................... 161 SWAPF .................................................................... 161 TRIS ......................................................................... 161 XORLW .................................................................... 162 XORWF .................................................................... 162 Section ..................................................................... 147 Summary Table ........................................................ 148 INT Interrupt ..................................................................... 143 INTCON ............................................................................. 29 INTCON Register ............................................................... 32 INTEDG bit ................................................................. 31, 143 Internal Sampling Switch (Rss) Impedance ..................... 120 Interrupts .......................................................................... 129 PortB Change .......................................................... 143 RB7:RB4 Port Change ............................................... 45 Section ..................................................................... 141 TMR0 ....................................................................... 143 IRP bit ................................................................................ 30 L Loading of PC .................................................................... 40 1997 Microchip Technology Inc. M MCLR .......................................................................133, 136 Memory Data Memory ..............................................................20 Program Memory ........................................................19 Program Memory Maps PIC16C72 ...........................................................19 PIC16C73 ...........................................................19 PIC16C73A ........................................................19 PIC16C74 ...........................................................19 PIC16C74A ........................................................19 PIC16C76 ...........................................................20 PIC16C77 ...........................................................20 Register File Maps PIC16C72 ...........................................................21 PIC16C73 ...........................................................21 PIC16C73A ........................................................21 PIC16C74 ...........................................................21 PIC16C74A ........................................................21 PIC16C76 ...........................................................21 PIC16C77 ...........................................................21 MPASM Assembler ..........................................................163 MPLAB-C ..........................................................................165 MPSIM Software Simulator ......................................163, 165 O OERR bit ..........................................................................100 OPCODE ..........................................................................147 OPTION ..............................................................................29 OPTION Register ...............................................................31 Orthogonal ............................................................................9 OSC selection ...................................................................129 Oscillator HS .....................................................................131, 135 LP .....................................................................131, 135 RC ............................................................................131 XT .....................................................................131, 135 Oscillator Configurations ..................................................131 Output of TMR2 ..................................................................69 P P ...................................................................................78, 83 Packaging 28-Lead Ceramic w/Window .....................................251 28-Lead PDIP ...........................................................253 28-Lead SOIC ...........................................................255 28-Lead SSOP .........................................................256 40-Lead CERDIP w/Window ....................................252 40-Lead PDIP ...........................................................254 44-Lead MQFP .........................................................258 44-Lead PLCC ..........................................................257 44-Lead TQFP ..........................................................259 Paging, Program Memory ...................................................40 Parallel Slave Port ........................................................50, 54 PCFG0 bit .........................................................................118 PCFG1 bit .........................................................................118 PCFG2 bit .........................................................................118 PCL Register ............................23, 24, 25, 26, 27, 28, 29, 40 PCLATH ...........................................................................136 PCLATH Register .....................23, 24, 25, 26, 27, 28, 29, 40 PCON Register .....................................................29, 39, 135 PD bit ..................................................................30, 133, 135 PICDEM-1 Low-Cost PIC16/17 Demo Board ...........163, 164 PICDEM-2 Low-Cost PIC16CXX Demo Board .........163, 164 PICDEM-3 Low-Cost PIC16C9XXX Demo Board ............164 PICMASTER In-Circuit Emulator ......................................163 DS30390E-page 275 PIC16C7X PICSTART Low-Cost Development System .................... 163 PIE1 Register ............................................................... 29, 33 PIE2 Register ............................................................... 29, 37 Pin Compatible Devices ................................................... 271 Pin Functions MCLR/VPP ...................................................... 13, 14, 15 OSC1/CLKIN .................................................. 13, 14, 15 OSC2/CLKOUT .............................................. 13, 14, 15 RA0/AN0 ........................................................ 13, 14, 15 RA1/AN1 ........................................................ 13, 14, 15 RA2/AN2 ........................................................ 13, 14, 15 RA3/AN3/VREF ............................................... 13, 14, 15 RA4/T0CKI ..................................................... 13, 14, 15 RA5/AN4/SS .................................................. 13, 14, 15 RB0/INT ......................................................... 13, 14, 15 RB1 ................................................................ 13, 14, 15 RB2 ................................................................ 13, 14, 15 RB3 ................................................................ 13, 14, 15 RB4 ................................................................ 13, 14, 15 RB5 ................................................................ 13, 14, 15 RB6 ................................................................ 13, 14, 15 RB7 ................................................................ 13, 14, 15 RC0/T1OSO/T1CKI ....................................... 13, 14, 16 RC1/T1OSI ................................................................ 13 RC1/T1OSI/CCP2 ................................................ 14, 16 RC2/CCP1 ..................................................... 13, 14, 16 RC3/SCK/SCL ............................................... 13, 14, 16 RC4/SDI/SDA ................................................ 13, 14, 16 RC5/SDO ....................................................... 13, 14, 16 RC6 ............................................................................ 13 RC6/TX/CK ............................................ 14, 16, 99-114 RC7 ............................................................................ 13 RC7/RX/DT ............................................ 14, 16, 99-114 RD0/PSP0 .................................................................. 16 RD1/PSP1 .................................................................. 16 RD2/PSP2 .................................................................. 16 RD3/PSP3 .................................................................. 16 RD4/PSP4 .................................................................. 16 RD5/PSP5 .................................................................. 16 RD6/PSP6 .................................................................. 16 RD7/PSP7 .................................................................. 16 RE0/RD/AN5 .............................................................. 16 RE1/WR/AN6 ............................................................. 16 RE2/CS/AN7 .............................................................. 16 SCK ...................................................................... 80-82 SDI ....................................................................... 80-82 SDO ..................................................................... 80-82 SS ........................................................................ 80-82 VDD ................................................................ 13, 14, 16 VSS ................................................................. 13, 14, 16 Pinout Descriptions PIC16C72 .................................................................. 13 PIC16C73 .................................................................. 14 PIC16C73A ................................................................ 14 PIC16C74 .................................................................. 15 PIC16C74A ................................................................ 15 PIC16C76 .................................................................. 14 PIC16C77 .................................................................. 15 PIR1 Register ..................................................................... 35 PIR2 Register ..................................................................... 38 POP .................................................................................... 40 DS30390E-page 276 POR ......................................................................... 134, 135 Oscillator Start-up Timer (OST) ....................... 129, 134 Power Control Register (PCON) .............................. 135 Power-on Reset (POR) ............................ 129, 134, 136 Power-up Timer (PWRT) ................................. 129, 134 Power-Up-Timer (PWRT) ........................................ 134 Time-out Sequence ................................................. 135 Time-out Sequence on Power-up ............................ 139 TO .................................................................... 133, 135 POR bit ...................................................................... 39, 135 Port RB Interrupt .............................................................. 143 PORTA ...................................................................... 29, 136 PORTA Register .............................................. 23, 25, 27, 43 PORTB ...................................................................... 29, 136 PORTB Register .............................................. 23, 25, 27, 45 PORTC ...................................................................... 29, 136 PORTC Register .............................................. 23, 25, 27, 48 PORTD ...................................................................... 29, 136 PORTD Register .................................................... 25, 27, 50 PORTE ...................................................................... 29, 136 PORTE Register .................................................... 25, 27, 51 Power-down Mode (SLEEP) ............................................ 145 PR2 .................................................................................... 29 PR2 Register ......................................................... 26, 28, 69 Prescaler, Switching Between Timer0 and WDT ............... 63 PRO MATE Universal Programmer ................................. 163 Program Branches ............................................................... 9 Program Memory Paging ....................................................................... 40 Program Memory Maps PIC16C72 .................................................................. 19 PIC16C73 .................................................................. 19 PIC16C73A ................................................................ 19 PIC16C74 .................................................................. 19 PIC16C74A ................................................................ 19 Program Verification ........................................................ 146 PS0 bit ............................................................................... 31 PS1 bit ............................................................................... 31 PS2 bit ............................................................................... 31 PSA bit ............................................................................... 31 PSPIE bit ........................................................................... 34 PSPIF bit ............................................................................ 36 PSPMODE bit ........................................................ 50, 51, 54 PUSH ................................................................................. 40 R R/W .............................................................................. 78, 83 R/W bit ............................................................. 90, 94, 95, 96 RBIF bit ...................................................................... 45, 143 RBPU bit ............................................................................ 31 RC Oscillator ............................................................ 132, 135 RCIE bit ............................................................................. 34 RCIF bit .............................................................................. 36 RCREG .............................................................................. 29 RCSTA Register ........................................................ 29, 100 RCV_MODE ...................................................................... 98 RD pin ................................................................................ 54 Read/Write bit Information, R/W .................................. 78, 83 Read-Modify-Write ............................................................. 53 Receive Overflow Detect bit, SSPOV ................................ 79 Receive Overflow Indicator bit, SSPOV ............................. 84 Register File ....................................................................... 20 1997 Microchip Technology Inc. PIC16C7X Registers FSR Summary ........................................................... 29 INDF Summary ........................................................... 29 Initialization Conditions ............................................ 136 INTCON Summary ........................................................... 29 Maps PIC16C72 .......................................................... 21 PIC16C73 .......................................................... 21 PIC16C73A ........................................................ 21 PIC16C74 .......................................................... 21 PIC16C74A ........................................................ 21 PIC16C76 .......................................................... 22 PIC16C77 .......................................................... 22 OPTION Summary ........................................................... 29 PCL Summary ........................................................... 29 PCLATH Summary ........................................................... 29 PORTB Summary ........................................................... 29 Reset Conditions ...................................................... 136 SSPBUF Section ............................................................... 80 SSPCON Diagram ............................................................. 79 SSPSR Section ............................................................... 80 SSPSTAT ................................................................... 83 Diagram ............................................................. 78 Section ............................................................... 78 STATUS Summary ........................................................... 29 Summary .............................................................. 25, 27 TMR0 Summary ........................................................... 29 TRISB Summary ........................................................... 29 Reset ........................................................................ 129, 133 Reset Conditions for Special Registers ........................... 136 RP0 bit ......................................................................... 20, 30 RP1 bit ............................................................................... 30 RX9 bit ............................................................................. 100 RX9D bit ........................................................................... 100 S S ................................................................................... 78, 83 SCK .................................................................................... 80 SCL .................................................................................... 94 SDI ..................................................................................... 80 SDO ................................................................................... 80 Serial Communication Interface (SCI) Module, See USART Services One-Time-Programmable (OTP) ................................. 7 Quick-Turnaround-Production (QTP) ........................... 7 Serialized Quick-Turnaround Production (SQTP) ........ 7 Slave Mode SCL ............................................................................ 94 SDA ............................................................................ 94 SLEEP ..................................................................... 129, 133 SMP ................................................................................... 83 Software Simulator (MPSIM) ........................................... 165 SPBRG .............................................................................. 29 1997 Microchip Technology Inc. SPBRG Register ...........................................................26, 28 Special Event Trigger .......................................................125 Special Features of the CPU ............................................129 Special Function Registers PIC16C72 ...................................................................23 PIC16C73 .............................................................25, 27 PIC16C73A ...........................................................25, 27 PIC16C74 .............................................................25, 27 PIC16C74A ...........................................................25, 27 PIC16C76 ...................................................................27 PIC16C77 ...................................................................27 Special Function Registers, Section ...................................23 SPEN bit ...........................................................................100 SPI Block Diagram ......................................................80, 85 Master Mode ...............................................................86 Master Mode Timing ...................................................87 Mode ...........................................................................80 Serial Clock ................................................................85 Serial Data In ..............................................................85 Serial Data Out ...........................................................85 Slave Mode Timing .....................................................88 Slave Mode Timing Diagram ......................................87 Slave Select ................................................................85 SPI clock .....................................................................86 SPI Mode ....................................................................85 SSPCON ....................................................................84 SSPSTAT ...................................................................83 SPI Clock Edge Select bit, CKE .........................................83 SPI Data Input Sample Phase Select bit, SMP ..................83 SPI Mode ............................................................................80 SREN bit ...........................................................................100 SS .......................................................................................80 SSP Module Overview ........................................................77 Section ........................................................................77 SSPBUF .....................................................................86 SSPCON ....................................................................84 SSPSR .......................................................................86 SSPSTAT ...................................................................83 SSP in I2C Mode - See I2C SSPADD .............................................................................93 SSPADD Register ............................................24, 26, 28, 29 SSPBUF .......................................................................29, 93 SSPBUF Register .........................................................25, 27 SSPCON ......................................................................79, 84 SSPCON Register ........................................................25, 27 SSPEN .........................................................................79, 84 SSPIE bit ............................................................................33 SSPIF bit ......................................................................35, 36 SSPM3:SSPM0 ............................................................79, 84 SSPOV ...................................................................79, 84, 94 SSPSTAT .....................................................................78, 93 SSPSTAT Register .....................................24, 26, 28, 29, 83 Stack ...................................................................................40 Overflows ....................................................................40 Underflow ...................................................................40 Start bit, S .....................................................................78, 83 STATUS Register .........................................................29, 30 Stop bit, P .....................................................................78, 83 Synchronous Serial Port (SSP) Block Diagram, SPI Mode ..........................................80 SPI Master/Slave Diagram .........................................81 SPI Mode ....................................................................80 Synchronous Serial Port Enable bit, SSPEN ................79, 84 DS30390E-page 277 PIC16C7X Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 ............................................................ 79, 84 Synchronous Serial Port Module ........................................ 77 Synchronous Serial Port Status Register ........................... 83 T T0CS bit ............................................................................. 31 T1CKPS0 bit ...................................................................... 65 T1CKPS1 bit ...................................................................... 65 T1CON ............................................................................... 29 T1CON Register ........................................................... 29, 65 T1OSCEN bit ..................................................................... 65 T1SYNC bit ........................................................................ 65 T2CKPS0 bit ...................................................................... 70 T2CKPS1 bit ...................................................................... 70 T2CON Register ........................................................... 29, 70 TAD ................................................................................... 121 Timer Modules, Overview .................................................. 57 Timer0 RTCC ....................................................................... 136 Timers Timer0 Block Diagram .................................................... 59 External Clock .................................................... 61 External Clock Timing ........................................ 61 Increment Delay ................................................. 61 Interrupt .............................................................. 59 Interrupt Timing .................................................. 60 Overview ............................................................ 57 Prescaler ............................................................ 62 Prescaler Block Diagram ................................... 62 Section ............................................................... 59 Switching Prescaler Assignment ........................ 63 Synchronization ................................................. 61 T0CKI ................................................................. 61 T0IF .................................................................. 143 Timing ................................................................ 59 TMR0 Interrupt ................................................. 143 Timer1 Asynchronous Counter Mode ............................ 67 Block Diagram .................................................... 66 Capacitor Selection ............................................ 67 External Clock Input ........................................... 66 External Clock Input Timing ............................... 67 Operation in Timer Mode ................................... 66 Oscillator ............................................................ 67 Overview ............................................................ 57 Prescaler ...................................................... 66, 68 Resetting of Timer1 Registers ........................... 68 Resetting Timer1 using a CCP Trigger Output .. 68 Synchronized Counter Mode ............................. 66 T1CON ............................................................... 65 TMR1H ............................................................... 67 TMR1L ............................................................... 67 Timer2 Block Diagram .................................................... 69 Module ............................................................... 69 Overview ............................................................ 57 Postscaler .......................................................... 69 Prescaler ............................................................ 69 T2CON ............................................................... 70 Timing Diagrams A/D Conversion ................................ 182, 200, 218, 239 Brown-out Reset .............................. 134, 175, 209, 228 Capture/Compare/PWM ................... 177, 193, 211, 230 CLKOUT and I/O .............................. 174, 190, 208, 227 DS30390E-page 278 External Clock Timing ...................... 173, 189, 207, 226 I2C Bus Data .................................... 180, 197, 215, 236 I2C Bus Start/Stop bits ..................... 179, 196, 214, 235 I2C Clock Synchronization ......................................... 92 I2C Data Transfer Wait State ..................................... 90 I2C Multi-Master Arbitration ....................................... 92 I2C Reception (7-bit Address) .................................... 95 Parallel Slave Port ................................................... 194 Power-up Timer ............................... 175, 191, 209, 228 Reset ............................................... 175, 191, 209, 228 SPI Master Mode ....................................................... 87 SPI Mode ................................................. 178, 195, 213 SPI Mode, Master/Slave Mode, No SS Control ......... 82 SPI Mode, Slave Mode With SS Control ................... 82 SPI Slave Mode (CKE = 1) ........................................ 88 SPI Slave Mode Timing (CKE = 0) ............................ 87 Start-up Timer .................................. 175, 191, 209, 228 Time-out Sequence ................................................. 139 Timer0 ....................................... 59, 176, 192, 210, 229 Timer0 Interrupt Timing ............................................. 60 Timer0 with External Clock ........................................ 61 Timer1 ............................................. 176, 192, 210, 229 USART Asynchronous Master Transmission .......... 107 USART Asynchronous Reception ........................... 108 USART RX Pin Sampling ................................ 104, 105 USART Synchronous Receive ................ 198, 216, 237 USART Synchronous Reception ............................. 113 USART Synchronous Transmission 111, 198, 216, 237 Wake-up from Sleep via Interrupt ............................ 146 Watchdog Timer .............................. 175, 191, 209, 228 TMR0 ................................................................................. 29 TMR0 Register ............................................................. 25, 27 TMR1CS bit ....................................................................... 65 TMR1H .............................................................................. 29 TMR1H Register .................................................... 23, 25, 27 TMR1IE bit ......................................................................... 33 TMR1IF bit ................................................................... 35, 36 TMR1L ............................................................................... 29 TMR1L Register ..................................................... 23, 25, 27 TMR1ON bit ....................................................................... 65 TMR2 ................................................................................. 29 TMR2 Register ....................................................... 23, 25, 27 TMR2IE bit ......................................................................... 33 TMR2IF bit ................................................................... 35, 36 TMR2ON bit ....................................................................... 70 TO bit ................................................................................. 30 TOUTPS0 bit ..................................................................... 70 TOUTPS1 bit ..................................................................... 70 TOUTPS2 bit ..................................................................... 70 TOUTPS3 bit ..................................................................... 70 TRISA ................................................................................ 29 TRISA Register ................................................ 24, 26, 28, 43 TRISB ................................................................................ 29 TRISB Register ................................................ 24, 26, 28, 45 TRISC ................................................................................ 29 TRISC Register ................................................ 24, 26, 28, 48 TRISD ................................................................................ 29 TRISD Register ...................................................... 26, 28, 50 TRISE ................................................................................ 29 TRISE Register ...................................................... 26, 28, 51 Two's Complement .............................................................. 9 TXIE bit .............................................................................. 34 TXIF bit .............................................................................. 36 TXREG .............................................................................. 29 TXSTA ............................................................................... 29 TXSTA Register ................................................................. 99 1997 Microchip Technology Inc. PIC16C7X U UA ................................................................................ 78, 83 Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................................ 99 Update Address bit, UA ............................................... 78, 83 USART Asynchronous Mode ................................................ 106 Asynchronous Receiver ........................................... 108 Asynchronous Reception ......................................... 109 Asynchronous Transmission .................................... 107 Asynchronous Transmitter ....................................... 106 Baud Rate Generator (BRG) .................................... 101 Receive Block Diagram ............................................ 108 Sampling .................................................................. 104 Synchronous Master Mode ...................................... 110 Synchronous Master Reception ............................... 112 Synchronous Master Transmission .......................... 110 Synchronous Slave Mode ........................................ 114 Synchronous Slave Reception ................................. 114 Synchronous Slave Transmit ................................... 114 Transmit Block Diagram ........................................... 106 UV Erasable Devices ........................................................... 7 W W Register ALU .............................................................................. 9 Wake-up from SLEEP ...................................................... 145 Watchdog Timer (WDT) ........................... 129, 133, 136, 144 WCOL .......................................................................... 79, 84 WDT ................................................................................. 136 Block Diagram .......................................................... 144 Period ....................................................................... 144 Programming Considerations .................................. 144 Timeout .................................................................... 136 Word ................................................................................ 129 WR pin ............................................................................... 54 Write Collision Detect bit, WCOL ................................. 79, 84 LIST OF EXAMPLES Example 3-1: Example 4-1: Example 4-2: Example 5-1: Example 5-2: Example 5-3: Example 5-4: Example 7-1: Example 7-2: Example 8-1: Example 10-1: Example 10-2: Example 11-1: Example 11-2: Example 12-1: Equation 13-1: Example 13-1: Example 13-2: Example 13-3: Example 14-1: Instruction Pipeline Flow............................17 Call of a Subroutine in Page 1 from Page 0 ..............................................41 Indirect Addressing ....................................41 Initializing PORTA......................................43 Initializing PORTB......................................45 Initializing PORTC .....................................48 Read-Modify-Write Instructions on an I/O Port ............................................53 Changing Prescaler (Timer0WDT).........63 Changing Prescaler (WDTTimer0).........63 Reading a 16-bit Free-Running Timer .......67 Changing Between Capture Prescalers.................................................73 PWM Period and Duty Cycle Calculation .................................................75 Loading the SSPBUF (SSPSR) Register ....................................................80 Loading the SSPBUF (SSPSR) Register (PIC16C76/77) ...........................85 Calculating Baud Rate Error ....................101 A/D Minimum Charging Time...................120 Calculating the Minimum Required Acquisition Time .....................................120 A/D Conversion........................................122 4-bit vs. 8-bit Conversion Times ..............123 Saving STATUS, W, and PCLATH Registers in RAM.....................................143 X XMIT_MODE ...................................................................... 98 Z Z bit .................................................................................... 30 Zero bit ................................................................................. 9 1997 Microchip Technology Inc. DS30390E-page 279 PIC16C7X LIST OF FIGURES Figure 8-1: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 4-1: Figure 8-2: Figure 9-1: Figure 9-2: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 4-12: Figure 4-13: Figure 4-14: Figure 4-15: Figure 4-16: Figure 4-17: Figure 4-18: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 5-6: Figure 5-7: Figure 5-8: Figure 5-9: Figure 5-10: Figure 5-11: Figure 5-12: Figure 5-13: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: PIC16C72 Block Diagram ......................... 10 PIC16C73/73A/76 Block Diagram............. 11 PIC16C74/74A/77 Block Diagram............. 12 Clock/Instruction Cycle.............................. 17 PIC16C72 Program Memory Map and Stack .................................................. 19 PIC16C73/73A/74/74A Program Memory Map and Stack ............................ 19 PIC16C76/77 Program Memory Map and Stack .......................................... 20 PIC16C72 Register File Map .................... 21 PIC16C73/73A/74/74A Register File Map .................................................... 21 PIC16C76/77 Register File Map ............... 22 Status Register (Address 03h, 83h, 103h, 183h) ...................................... 30 OPTION Register (Address 81h, 181h) ......................................................... 31 INTCON Register (Address 0Bh, 8Bh, 10bh, 18bh)............... 32 PIE1 Register PIC16C72 (Address 8Ch) ........................................... 33 PIE1 Register PIC16C73/73A/ 74/74A/76/77 (Address 8Ch)..................... 34 PIR1 Register PIC16C72 (Address 0Ch) ........................................... 35 PIR1 Register PIC16C73/73A/ 74/74A/76/77 (Address 0Ch)..................... 36 PIE2 Register (Address 8Dh).................... 37 PIR2 Register (Address 0Dh).................... 38 PCON Register (Address 8Eh) ................. 39 Loading of PC In Different Situations .................................................. 40 Direct/Indirect Addressing ......................... 41 Block Diagram of RA3:RA0 and RA5 Pins ............................................ 43 Block Diagram of RA4/T0CKI Pin ............. 43 Block Diagram of RB3:RB0 Pins............... 45 Block Diagram of RB7:RB4 Pins (PIC16C73/74) .......................................... 46 Block Diagram of RB7:RB4 Pins (PIC16C72/73A/ 74A/76/77)................................................. 46 PORTC Block Diagram (Peripheral Output Override).................... 48 PORTD Block Diagram (in I/O Port Mode)..................................... 50 PORTE Block Diagram (in I/O Port Mode)..................................... 51 TRISE Register (Address 89h).................. 51 Successive I/O Operation ......................... 53 PORTD and PORTE Block Diagram (Parallel Slave Port) .................................. 54 Parallel Slave Port Write Waveforms ........ 55 Parallel Slave Port Read Waveforms........ 55 Timer0 Block Diagram............................... 59 Timer0 Timing: Internal Clock/No Prescale .................................................... 59 Timer0 Timing: Internal Clock/Prescale 1:2 .................................... 60 Timer0 Interrupt Timing............................. 60 Timer0 Timing with External Clock............ 61 Block Diagram of the Timer0/WDT Prescaler ................................................... 62 DS30390E-page 280 Figure 10-1: Figure 10-2: Figure 10-3: Figure 10-4: Figure 10-5: Figure 11-1: Figure 11-2: Figure 11-3: Figure 11-4: Figure 11-5: Figure 11-6: Figure 11-7: Figure 11-8: Figure 11-9: Figure 11-10: Figure 11-11: Figure 11-12: Figure 11-13: Figure 11-14: Figure 11-15: Figure 11-16: Figure 11-17: Figure 11-18: Figure 11-19: Figure 11-20: Figure 11-21: Figure 11-22: Figure 11-23: Figure 11-24: Figure 11-25: Figure 11-26: Figure 11-27: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: T1CON: Timer1 Control Register (Address 10h) .......................................... 65 Timer1 Block Diagram .............................. 66 Timer2 Block Diagram .............................. 69 T2CON: Timer2 Control Register (Address 12h) .......................................... 70 CCP1CON Register (Address 17h)/ CCP2CON Register (Address 1Dh).......... 72 Capture Mode Operation Block Diagram .......................................... 72 Compare Mode Operation Block Diagram .......................................... 73 Simplified PWM Block Diagram ................ 74 PWM Output ............................................. 74 SSPSTAT: Sync Serial Port Status Register (Address 94h)............................. 78 SSPCON: Sync Serial Port Control Register (Address 14h)............................. 79 SSP Block Diagram (SPI Mode) ............... 80 SPI Master/Slave Connection................... 81 SPI Mode Timing, Master Mode or Slave Mode w/o SS Control.................. 82 SPI Mode Timing, Slave Mode with SS Control ................................................ 82 SSPSTAT: Sync Serial Port Status Register (Address 94h)(PIC16C76/77)..... 83 SSPCON: Sync Serial Port Control Register (Address 14h)(PIC16C76/77)..... 84 SSP Block Diagram (SPI Mode) (PIC16C76/77).......................................... 85 SPI Master/Slave Connection PIC16C76/77) ........................................... 86 SPI Mode Timing, Master Mode (PIC16C76/77)......................................... 87 SPI Mode Timing (Slave Mode With CKE = 0) (PIC16C76/77) ................. 87 SPI Mode Timing (Slave Mode With CKE = 1) (PIC16C76/77) .................. 88 Start and Stop Conditions......................... 89 7-bit Address Format ................................ 90 I2C 10-bit Address Format ........................ 90 Slave-receiver Acknowledge .................... 90 Data Transfer Wait State .......................... 90 Master-transmitter Sequence ................... 91 Master-receiver Sequence........................ 91 Combined Format ..................................... 91 Multi-master Arbitration (Two Masters)........................................... 92 Clock Synchronization .............................. 92 SSP Block Diagram (I2C Mode) ................................................ 93 I2C Waveforms for Reception (7-bit Address) .......................................... 95 I2C Waveforms for Transmission (7-bit Address) .......................................... 96 Operation of the I2C Module in IDLE_MODE, RCV_MODE or XMIT_MODE ............................................ 98 TXSTA: Transmit Status and Control Register (Address 98h) ................ 99 RCSTA: Receive Status and Control Register (Address 18h) .............. 100 RX Pin Sampling Scheme. BRGH = 0 (PIC16C73/73A/74/74A) ......................... 104 RX Pin Sampling Scheme, BRGH = 1 (PIC16C73/73A/74/74A) ......................... 104 1997 Microchip Technology Inc. PIC16C7X Figure 12-5: Figure 12-6: Figure 12-7: Figure 12-8: Figure 12-9: Figure 12-10: Figure 12-11: Figure 12-12: Figure 12-13: Figure 12-14: Figure 13-1: Figure 13-2: Figure 13-3: Figure 13-4: Figure 13-5: Figure 13-6: Figure 14-1: Figure 14-2: Figure 14-3: Figure 14-4: Figure 14-5: Figure 14-6: Figure 14-7: Figure 14-8: Figure 14-9: Figure 14-10: Figure 14-11: Figure 14-12: Figure 14-13: Figure 14-14: Figure 14-15: Figure 14-16: Figure 14-17: Figure 14-18: Figure 14-19: Figure 14-20: Figure 14-21: Figure 15-1: Figure 17-1: Figure 17-2: Figure 17-3: RX Pin Sampling Scheme, BRGH = 1 (PIC16C73/73A/74/74A) ......................... 104 RX Pin Sampling Scheme, BRGH = 0 OR BRGH = 1 ( PIC16C76/77) ......................................... 105 USART Transmit Block Diagram............. 106 Asynchronous Master Transmission ....... 107 Asynchronous Master Transmission (Back to Back)......................................... 107 USART Receive Block Diagram.............. 108 Asynchronous Reception ........................ 108 Synchronous Transmission..................... 111 Synchronous Transmission (Through TXEN)...................................... 111 Synchronous Reception (Master Mode, SREN)............................. 113 ADCON0 Register (Address 1Fh) ........... 117 ADCON1 Register (Address 9Fh) ........... 118 A/D Block Diagram.................................. 119 Analog Input Model ................................. 120 A/D Transfer Function ............................. 125 Flowchart of A/D Operation..................... 126 Configuration Word for PIC16C73/74........................................... 129 Configuration Word for PIC16C72/73A/74A/76/77....................... 130 Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration)................................. 131 External Clock Input Operation (HS, XT or LP OSC Configuration) ......... 131 External Parallel Resonant Crystal Oscillator Circuit ...................................... 132 External Series Resonant Crystal Oscillator Circuit ..................................... 132 RC Oscillator Mode ................................. 132 Simplified Block Diagram of On-chip Reset Circuit............................................ 133 Brown-out Situations ............................... 134 Time-out Sequence on Power-up (MCLR not Tied to VDD): Case 1............. 139 Time-out Sequence on Power-up (MCLR Not Tied To VDD): Case 2.......... 139 Time-out Sequence on Power-up (MCLR Tied to VDD) ................................ 139 External Power-on Reset Circuit (for Slow VDD Power-up)......................... 140 External Brown-out Protection Circuit 1 ................................................... 140 External Brown-out Protection Circuit 2 ................................................... 140 Interrupt Logic ......................................... 142 INT Pin Interrupt Timing .......................... 142 Watchdog Timer Block Diagram ............. 144 Summary of Watchdog Timer Registers....................................... 144 Wake-up from Sleep Through Interrupt................................................... 146 Typical In-Circuit Serial Programming Connection ....................... 146 General Format for Instructions .............. 147 Load Conditions ...................................... 172 External Clock Timing ............................. 173 CLKOUT and I/O Timing ......................... 174 Figure 17-4: Figure 17-5: Figure 17-6: Figure 17-7: Figure 17-8: Figure 17-9: Figure 17-10: Figure 17-11: Figure 18-1: Figure 18-2: Figure 18-3: Figure 18-4: Figure 18-5: Figure 18-6: Figure 18-7: Figure 18-8: Figure 18-9: Figure 18-10: Figure 18-11: Figure 18-12: Figure 18-13: Figure 19-1: Figure 19-2: Figure 19-3: Figure 19-4: Figure 19-5: Figure 19-6: Figure 19-7: Figure 19-8: Figure 19-9: Figure 19-10: Figure 19-11: Figure 19-12: Figure 19-13: Figure 19-14: Figure 20-1: Figure 20-2: Figure 20-3: Figure 20-4: Figure 20-5: Figure 20-6: Figure 20-7: Figure 20-8: 1997 Microchip Technology Inc. Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ......................................................175 Brown-out Reset Timing ..........................175 Timer0 and Timer1 External Clock Timings .........................................176 Capture/Compare/PWM Timings (CCP1) .......................................177 SPI Mode Timing .....................................178 I2C Bus Start/Stop Bits Timing.................179 I2C Bus Data Timing ................................180 A/D Conversion Timing............................182 Load Conditions.......................................188 External Clock Timing..............................189 CLKOUT and I/O Timing..........................190 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing..................................................191 Timer0 and Timer1 External Clock Timings .........................................192 Capture/Compare/PWM Timings (CCP1 and CCP2) ...................................193 Parallel Slave Port Timing (PIC16C74)..............................................194 SPI Mode Timing .....................................195 I2C Bus Start/Stop Bits Timing.................196 I2C Bus Data Timing ................................197 USART Synchronous Transmission (Master/Slave) Timing..............................198 USART Synchronous Receive (Master/Slave) Timing..............................198 A/D Conversion Timing............................200 Load Conditions.......................................206 External Clock Timing..............................207 CLKOUT and I/O Timing..........................208 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ...........................209 Brown-out Reset Timing ..........................209 Timer0 and Timer1 External Clock Timings .........................................210 Capture/Compare/PWM Timings (CCP1 and CCP2) ...................................211 Parallel Slave Port Timing (PIC16C74A) ...........................................212 SPI Mode Timing .....................................213 I2C Bus Start/Stop Bits Timing.................214 I2C Bus Data Timing ................................215 USART Synchronous Transmission (Master/Slave) Timing..............................216 USART Synchronous Receive (Master/Slave) Timing..............................216 A/D Conversion Timing............................218 Load Conditions.......................................225 External Clock Timing..............................226 CLKOUT and I/O Timing..........................227 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ...........................228 Brown-out Reset Timing ..........................228 Timer0 and Timer1 External Clock Timings ..........................................229 Capture/Compare/PWM Timings (CCP1 and CCP2) ...................................230 Parallel Slave Port Timing (PIC16C77).............................................231 DS30390E-page 281 PIC16C7X Figure 20-9: Figure 20-10: Figure 20-11: Figure 20-12: Figure 20-13: Figure 20-14: Figure 20-15: Figure 20-16: Figure 20-17: Figure 21-1: Figure 21-2: Figure 21-3: Figure 21-4: Figure 21-5: Figure 21-6: Figure 21-7: Figure 21-8: Figure 21-9: Figure 21-10: Figure 21-11: Figure 21-12: Figure 21-13: Figure 21-14: Figure 21-15: Figure 21-16: Figure 21-17: Figure 21-18: Figure 21-19: Figure 21-20: Figure 21-21: Figure 21-22: Figure 21-23: Figure 21-24: Figure 21-25: Figure 21-26: SPI Master Mode Timing (CKE = 0)........ 232 SPI Master Mode Timing (CKE = 1)........ 232 SPI Slave Mode Timing (CKE = 0).......... 233 SPI Slave Mode Timing (CKE = 1).......... 233 I2C Bus Start/Stop Bits Timing ................ 235 I2C Bus Data Timing ............................... 236 USART Synchronous Transmission (Master/Slave) Timing ............................. 237 USART Synchronous Receive (Master/Slave) Timing ............................. 237 A/D Conversion Timing ........................... 239 Typical IPD vs. VDD (WDT Disabled, RC Mode)................................................ 241 Maximum IPD vs. VDD (WDT Disabled, RC Mode)................................ 241 Typical IPD vs. VDD @ 25C (WDT Enabled, RC Mode)................................. 242 Maximum IPD vs. VDD (WDT Enabled, RC Mode)................................. 242 Typical RC Oscillator Frequency vs. VDD .................................. 242 Typical RC Oscillator Frequency vs. VDD .................................. 242 Typical RC Oscillator Frequency vs. VDD .................................. 242 Typical IPD vs. VDD Brown-out Detect Enabled (RC Mode) ..................... 243 Maximum IPD vs. VDD Brown-out Detect Enabled (85C to -40C, RC Mode) ...................... 243 Typical IPD vs. Timer1 Enabled (32 kHz, RC0/RC1= 33 pF/33 pF, RC Mode)................................................ 243 Maximum IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C to -40C, RC Mode) ....... 243 Typical IDD vs. Frequency (RC Mode @ 22 pF, 25C)...................... 244 Maximum IDD vs. Frequency (RC Mode @ 22 pF, -40C to 85C)........ 244 Typical IDD vs. Frequency (RC Mode @ 100 pF, 25C).................... 245 Maximum IDD vs. Frequency ( RC Mode @ 100 pF, -40C to 85C)....... 245 Typical IDD vs. Frequency (RC Mode @ 300 pF, 25C).................... 246 Maximum IDD vs. Frequency (RC Mode @ 300 pF, -40C to 85C)...... 246 Typical IDD vs. Capacitance @ 500 kHz (RC Mode) ................................ 247 Transconductance(gm) of HS Oscillator vs. VDD .............................. 247 Transconductance(gm) of LP Oscillator vs. VDD .................................... 247 Transconductance(gm) of XT Oscillator vs. VDD .................................... 247 Typical XTAL Startup Time vs. VDD (LP Mode, 25C) ..................................... 248 Typical XTAL Startup Time vs. VDD (HS Mode, 25C)..................................... 248 Typical XTAL Startup Time vs. VDD (XT Mode, 25C) ..................................... 248 Typical Idd vs. Frequency (LP Mode, 25C) ..................................... 249 Maximum IDD vs. Frequency (LP Mode, 85C to -40C) ....................... 249 DS30390E-page 282 Figure 21-27: Figure 21-28: Figure 21-29: Figure 21-30: Typical IDD vs. Frequency (XT Mode, 25C)..................................... 249 Maximum IDD vs. Frequency (XT Mode, -40C to 85C)....................... 249 Typical IDD vs. Frequency (HS Mode, 25C) .................................... 250 Maximum IDD vs. Frequency (HS Mode, -40C to 85C) ...................... 250 1997 Microchip Technology Inc. PIC16C7X LIST OF TABLES Table 12-8: Table 1-1: Table 3-1: Table 3-2: Table 3-3: Table 4-1: Table 12-9: Table 4-2: Table 4-3: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 5-5: Table 5-6: Table 5-7: Table 5-8: Table 5-9: Table 5-10: Table 5-11: Table 7-1: Table 8-1: Table 8-2: Table 9-1: Table 10-1: Table 10-2: Table 10-3: Table 10-4: Table 10-5: Table 11-1: Table 11-2: Table 11-3: Table 11-4: Table 11-5: Table 12-1: Table 12-2: Table 12-3: Table 12-4: Table 12-5: Table 12-6: Table 12-7: PIC16C7XX Family of Devces .................... 6 PIC16C72 Pinout Description ................... 13 PIC16C73/73A/76 Pinout Description ....... 14 PIC16C74/74A/77 Pinout Description ....... 15 PIC16C72 Special Function Register Summary................................................... 23 PIC16C73/73A/74/74A Special Function Register Summary...................... 25 PIC16C76/77 Special Function Register Summary .................................... 27 PORTA Functions ..................................... 44 Summary of Registers Associated with PORTA .............................................. 44 PORTB Functions ..................................... 46 Summary of Registers Associated with PORTB .............................................. 47 PORTC Functions ..................................... 48 Summary of Registers Associated with PORTC .............................................. 49 PORTD Functions ..................................... 50 Summary of Registers Associated with PORTD .............................................. 50 PORTE Functions ..................................... 52 Summary of Registers Associated with PORTE .............................................. 52 Registers Associated with Parallel Slave Port..................................... 55 Registers Associated with Timer0............. 63 Capacitor Selection for the Timer1 Oscillator ....................................... 67 Registers Associated with Timer1 as a Timer/Counter ................................... 68 Registers Associated with Timer2 as a Timer/Counter ....................... 70 CCP Mode - Timer Resource.................... 71 Interaction of Two CCP Modules .............. 71 Example PWM Frequencies and Resolutions at 20 MHz .............................. 75 Registers Associated with Capture, Compare, and Timer1 ............................... 75 Registers Associated with PWM and Timer2 ................................................ 76 Registers Associated with SPI Operation .................................................. 82 Registers Associated with SPI Operation (PIC16C76/77) ......................... 88 I2C Bus Terminology ................................. 89 Data Transfer Received Byte Actions ...................................................... 94 Registers Associated with I2C Operation .................................................. 97 Baud Rate Formula ................................. 101 Registers Associated with Baud Rate Generator ....................................... 101 Baud Rates for Synchronous Mode ........ 102 Baud Rates for Asynchronous Mode (BRGH = 0) ............................................. 102 Baud Rates for Asynchronous Mode (BRGH = 1) ............................................. 103 Registers Associated with Asynchronous Transmission ................... 107 Registers Associated with Asynchronous Reception ........................ 109 1997 Microchip Technology Inc. Table 12-10: Table 12-11: Table 13-1: Table 13-2: Table 13-3: Table 14-1: Table 14-2: Table 14-3: Table 14-4: Table 14-5: Table 14-6: Table 14-7: Table 14-8: Table 15-1: Table 15-2: Table 16-1: Table 17-1: Table 17-2: Table 17-3: Table 17-4: Table 17-5: Table 17-6: Table 17-7: Table 17-8: Table 17-9: Table 17-10: Table 17-11: Table 18-1: Registers Associated with Synchronous Master Transmission ......................................111 Registers Associated with Synchronous Master Reception ...........................................112 Registers Associated with Synchronous Slave Transmission ...........115 Registers Associated with Synchronous Slave Reception.................115 TAD vs. Device Operating Frequencies .............................................121 Registers/Bits Associated with A/D, PIC16C72 ................................................126 Summary of A/D Registers, PIC16C73/73A/74/74A/76/77 ..................127 Ceramic Resonators ................................131 Capacitor Selection for Crystal Oscillator..................................................131 Time-out in Various Situations, PIC16C73/74 ...........................................135 Time-out in Various Situations, PIC16C72/73A/74A/76/77 .......................135 Status Bits and Their Significance, PIC16C73/74 ...........................................135 Status Bits and Their Significance, PIC16C72/73A/74A/76/77 .......................136 Reset Condition for Special Registers..................................................136 Initialization Conditions for all Registers..................................................136 Opcode Field Descriptions.......................147 PIC16CXX Instruction Set .......................148 Development Tools from Microchip .........166 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) .............................167 External Clock Timing Requirements ..........................................173 CLKOUT and I/O Timing Requirements ..........................................174 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and brown-out Reset Requirements ..........................................175 Timer0 and Timer1 External Clock Requirements ................................176 Capture/Compare/PWM Requirements (CCP1) .............................177 SPI Mode Requirements..........................178 I2C Bus Start/Stop Bits Requirements ..........................................179 I2C Bus Data Requirements ....................180 A/D Converter Characteristics: PIC16C72-04 (Commercial, Industrial, Extended) PIC16C72-10 (Commercial, Industrial, Extended) PIC16C72-20 (Commercial, Industrial, Extended) PIC16LC72-04 (Commercial, Industrial)...........................181 A/D Conversion Requirements ................182 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) .............................183 DS30390E-page 283 PIC16C7X Table 18-2: Table 18-3: Table 18-4: Table 18-5: Table 18-6: Table 18-7: Table 18-8: Table 18-9: Table 18-10: Table 18-11: Table 18-12: Table 18-13: Table 18-14: Table 19-1: Table 19-2: Table 19-3: Table 19-4: Table 19-5: Table 19-6: Table 19-7: Table 19-8: Table 19-9: Table 19-10: Table 19-11: Table 19-12: Table 19-13: Table 19-14: external Clock Timing Requirements.......................................... 189 CLKOUT and I/O Timing Requirements.......................................... 190 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements......................................... 191 Timer0 and Timer1 External Clock Requirements.......................................... 192 Capture/Compare/PWM Requirements (CCP1 and CCP2) ........... 193 Parallel Slave Port Requirements (PIC16C74) ............................................. 194 SPI Mode Requirements ......................... 195 I2C Bus Start/Stop Bits Requirements.......................................... 196 I2C Bus Data Requirements.................... 197 USART Synchronous Transmission Requirements.......................................... 198 usart Synchronous Receive Requirements.......................................... 198 A/D Converter Characteristics:................ 199 PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) PIC16LC73/74-04 (Commercial, Industrial) .......................... 199 A/D Conversion Requirements................ 200 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices)............................. 201 External Clock Timing Requirements.......................................... 207 CLKOUT and I/O Timing Requirements.......................................... 208 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and brown-out reset Requirements......... 209 Timer0 and Timer1 External Clock Requirements.......................................... 210 Capture/Compare/PWM Requirements (CCP1 and CCP2) ........... 211 Parallel Slave Port Requirements (PIC16C74A)........................................... 212 SPI Mode Requirements ......................... 213 I2C Bus Start/Stop Bits Requirements .... 214 I2C Bus Data Requirements.................... 215 USART Synchronous Transmission Requirements.......................................... 216 USART Synchronous Receive Requirements.......................................... 216 A/D Converter Characteristics:................ 217 PIC16C73A/74A-04 (Commercial, Industrial, Extended) PIC16C73A/74A-10 (Commercial, Industrial, Extended) PIC16C73A/74A-20 (Commercial, Industrial, Extended) PIC16LC73A/74A-04 (Commercial, Industrial) .......................... 217 A/D Conversion Requirements................ 218 DS30390E-page 284 Table 20-1: Table 20-2: Table 20-3: Table 20-4: Table 20-5: Table 20-6: Table 20-7: Table 20-8: Table 20-9: Table 20-10: Table 20-11: Table 20-12: Table 20-13: Table 20-14: Table 21-1: Table 21-2: Table E-1: Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) ............................ 220 External Clock Timing Requirements ......................................... 226 CLKOUT and I/O Timing Requirements ......................................... 227 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and brown-out reset Requirements ......................................... 228 Timer0 and Timer1 External Clock Requirements ......................................... 229 Capture/Compare/PWM Requirements (CCP1 and CCP2)........... 230 Parallel Slave Port Requirements (PIC16C77)............................................. 231 SPI Mode requirements .......................... 234 I2C Bus Start/Stop Bits Requirements .... 235 I2C Bus Data Requirements ................... 236 USART Synchronous Transmission Requirements ......................................... 237 USART Synchronous Receive Requirements ......................................... 237 A/D Converter Characteristics: ............... 238 PIC16C76/77-04 (Commercial, Industrial, Extended) PIC16C76/77-10 (Commercial, Industrial, Extended) PIC16C76/77-20 (Commercial, Industrial, Extended) PIC16LC76/77-04 (Commercial, Industrial).......................... 238 A/D Conversion Requirements ............... 239 RC Oscillator Frequencies...................... 247 Capacitor Selection for Crystal Oscillators ............................................... 248 Pin Compatible Devices.......................... 271 1997 Microchip Technology Inc. PIC16C6X ON-LINE SUPPORT Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts. To provide you with the most responsive service possible, the Microchip systems team monitors the BBS, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how Microchip products provide project solutions. The web site, like the BBS, is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products Connecting to the Microchip BBS Connect worldwide to the Microchip BBS using either the Internet or the CompuServe communications network. Internet: You can telnet or ftp to the Microchip BBS at the address: mchipbbs.microchip.com CompuServe Communications Network: When using the BBS via the Compuserve Network, in most cases, a local call is your only expense. The Microchip BBS connection does not use CompuServe membership services, therefore you do not need CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS. 1996 Microchip Technology Inc. The procedure to connect will vary slightly from country to country. Please check with your local CompuServe agent for details if you have a problem. CompuServe service allow multiple users various baud rates depending on the local point of access. The following connect procedure applies in most locations. 1. Set your modem to 8-bit, No parity, and One stop (8N1). This is not the normal CompuServe setting which is 7E1. 2. Dial your local CompuServe access number. 3. Depress the <Enter> key and a garbage string will appear because CompuServe is expecting a 7E1 setting. 4. Type +, depress the <Enter> key and "Host Name:" will appear. 5. Type MCHIPBBS, depress the <Enter> key and you will be connected to the Microchip BBS. In the United States, to find the CompuServe phone number closest to you, set your modem to 7E1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. After the system responds with "Host Name:", type NETWORK, depress the <Enter> key and follow CompuServe's directions. For voice information (or calling from overseas), you may call (614) 723-1550 for your local CompuServe number. Microchip regularly uses the Microchip BBS to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for Microchip systems software products. For each SIG, a moderator monitors, scans, and approves or disapproves files submitted to the SIG. No executable files are accepted from the user community in general to limit the spread of computer viruses. Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world. 970301 Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB, are trademarks and SQTP is a service mark of Microchip in the U.S.A. fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated. All other trademarks mentioned herein are the property of their respective companies. DS30390E-page 285 PIC16C6X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C6X Y N Literature Number: DS30390E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30390E-page 286 1996 Microchip Technology Inc. PIC16C7X PIC16C7X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. Examples PART NO. -XX X /XX XXX Pattern: Package: Temperature Range: Frequency Range: Device QTP, SQTP, Code or Special Requirements a) JW = Windowed CERDIP PQ = MQFP (Metric PQFP) TQ = TQFP (Thin Quad Flatpack) SO = SOIC SP = Skinny plastic dip b) P = PDIP L = PLCC SS = SSOP = 0C to +70C I = -40C to +85C c) E = -40C to +125C 04 = 200 kHz (PIC16C7X-04) 04 = 4 MHz 10 = 10 MHz 20 = 20 MHz PIC16C7X :VDD range 4.0V to 6.0V PIC16C7XT :VDD range 4.0V to 6.0V (Tape/Reel) PIC16LC7X :VDD range 2.5V to 6.0V PIC16LC7XT :VDD range 2.5V to 6.0V (Tape/Reel) PIC16C72 - 04/P 301 Commercial Temp., PDIP Package, 4 MHz, normal VDD limits, QTP pattern #301 PIC16LC76 - 041/SO Industrial Temp., SOIC package, 4 MHz, extended VDD limits PIC16C74A - 10E/P Automotive Temp., PDIP package, 10 MHz, normal VDD limits * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. The Microchip Website at www.microchip.com 2. Your local Microchip sales office (see following page) 3. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 4. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. DS30390E-page 287 1997 Microchip Technology Inc. Note the following details of the code protection feature on PICmicro(R) MCUs. * * * * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K. 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B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 China - Shenzhen 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086 San Jose Hong Kong Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 New York Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Taiwan Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 01/18/02 2002 Microchip Technology Inc.